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參數(shù)資料
| 型號(hào)： | ISL6580CR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Integrated Power Stage |
| 中文描述： | 35 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC56 |
| 封裝： | 8 X 8 MM, PLASTIC, QFN-56 |
| 文件頁數(shù)： | 22/31頁 |
| 文件大?。?/td> | 1391K |
| 代理商： | ISL6580CR |
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22
The key characteristic for the low side MOSFET is the DC
Rdson resistance. It is important to get a very low Rdson
value for the low side FET. For the high side MOSFET, gate
charge requirements are the key characteristic. Large gate
charge and gate resistance increases switching losses.
Because the high side MOSFET is integrated within the
ISL6580, a very low gate resistance of less then 300mW is
present. In a discrete high side MOSFET solution, a typical
total gate resistance from the gate driver and including the
internal silicon gate resistance is 1.5 to 2W. The integrated
MOSFET in the ISL6580 is optimized for high switching
efficiency with a low gate capacitance.
Understanding the turn on and turn off event for a MOSFET
is important in understanding how to interpret a data sheet
and for troubleshooting methods for the low side MOSFET in
particular.
Switching of the MOSFET
The MOSFET is driven by the applied gate to source
voltage. When the gate voltage is initially applied, the
voltage potential begins to ramp across the gate to the
source, but no current flows until the intrinsic threshold
voltage level is achieved (Figure 35). During time t1, the gate
to source capacitance (C
GS
) charges and the drain to
source current (I
DS
) and gate to source voltage (V
GS
)
continue to ramp. The slope of the current is directly related
to the gate voltage rise time and the forward
transconductance of the device as follows:
where:
IC
= Drain Current
gm
= Forward Transconductance
V
DS
= Drain to Source Voltage
The gate to source voltage ramp during this time is:
where:
V
DS
= Drain to Source Voltage
V
GG
= Gate Supply Voltage
R
G
= Gate Resistance
Ciss
= Constant Input Capacitance
V
TH
= Threshold Voltage
I
C
= Collector Current
gm
= Forward Transconductance
Substituting equation 7 into equation 6 gives:
Once time t2 is reached, C
GS
has been fully charged. IDS
plateaus and V
DS
begins to ramp down. During time t2, the
gate to drain capacitance (C
GD
), also known as the Miller
capacitance, begins to charge. Once the Miller capacitance
is fully charged, V
GS
rises until it reaches the voltage level of
the gate supply.
FIGURE 34. POWER DISSIPATION FOR STATIC AND
DYNAMIC OPERATION
FIGURE 35. MOSFET TURN ON CURVES
dI
C
dt
--------
gm
dV
---------------
=
(EQ. 6)
dV
---------------
V
------------------–
V
iss
–
G
=
(EQ. 7)
V
plateau
V
TH
I
--------
+
=
(EQ. 8)
dI
C
dt
--------
gm
V
-------------–
V
ies
–
R
G
=
(EQ. 9)
ISL6580
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