參數(shù)資料
型號： ISL5216KIZ
廠商： INTERSIL CORP
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-196
文件頁數(shù)： 50/65頁
文件大小： 1076K
代理商： ISL5216KIZ
50
July 8, 2005
Electrical Specifications
V
CC1
= Core Supply: 2.5V
±
0.125V, V
CC2
= I/O Supply: 3.3
±
0.165V ,
T
A
= -40
o
C to 85
o
C Industrial
PARAMETER
SYMBOL
MIN
MAX
UNITS
INPUT AND CONTROL TIMING (FIGURE 3)
CLK Frequency
f
CLK
t
CH
t
CL
t
DS
t
DH
t
PDC
t
RW
t
RS
-
95
MHz
CLK High (Note 25)
4.2
-
ns
CLK Low
(Note 25)
4.2
-
ns
Setup Time - Data Inputs, Input Enables, SYNCI, SYNCI(0-3) to CLK High
4
-
ns
Hold Time - Data Inputs, Input Enables, SYNCI, SYNCI(0-3) to CLK High
-0.5
-
ns
CLK to Output Valid - SYNCO, INTRPT
-
6.5
ns
RESET Pulse Width Low
5
-
ns
RESET Setup Time to CLK High (Note 24)
4
-
ns
MICROPROCESSOR WRITE TIMING (
μ
P MODE = 0, FIGURE 7)
P(15:0) Setup Time to Rising Edge of WR
t
PSW
t
PHW
t
ASW
t
AHW
t
CSW
t
CHW
t
WL
t
WH
7
-
ns
P(15:0) Hold Time from Rising Edge of WR
-1
-
ns
A(1:0) Setup Time to Rising Edge of WR
8
-
ns
A(1:0) Hold Time from Rising Edge of WR
-1
-
ns
CE Setup Time to Rising Edge of WR
8
-
ns
CE Hold Time from Rising Edge of WR
-1
-
ns
WR Low Time
5
-
ns
WR High to CLK High (Note 25)
2
-
ns
MICROPROCESSOR READ TIMING (
μ
P MODE = 0, FIGURE 8)
A(1:0) Hold Time from RISING Edge of RD (only applies when ADD(1:0) = 2)
t
AHR
t
DV
t
RE
t
RD
t
CSF
t
CHR
t
RCY
-2
-
ns
A(1:0) to P(15:0) Data Valid Time
-
16
ns
RD Low to P(15:0) Valid
-
11
ns
RD Disable Time (Note 25)
-
7
ns
CE to P(15:0) Data Valid Time
-
16
ns
CE Hold Time from Rising Edge of RD (only applies when ADD(1:0) = 2)
-2
-
ns
RD Cycle Time for ADD(1:0) = 2 (Note 25)
16
ns
MICROPROCESSOR WRITE TIMING (
μ
P MODE = 1, FIGURE 9)
P(15:0) Setup Time to Rising Edge of DSTRB
t
PSR
t
PHR
t
ASR
t
AHR
t
CSR
t
CHR
t
R/WSF
t
R/WHR
t
DW
t
DSTH
6
-
ns
P(15:0) Hold Time from Rising Edge of DSTRB
-1
-
ns
A(1:0) Setup Time to Rising Edge of DSTRB
8
-
ns
A(1:0) Hold Time from Rising Edge of DSTRB
-1
-
ns
CE Setup Time to Rising Edge of DSTRB
8
-
ns
CE Hold Time from Rising Edge of DSTRB
-1
-
ns
R/W Setup Time to Falling Edge of DSTRB
1
-
ns
R/W Hold Time from Rising Edge of DSTRB
0
-
ns
DSTRB Low Time
5
-
ns
DSTRB High to CLK High (Note 25)
2
-
ns
MICROPROCESSOR READ TIMING (
μ
P MODE = 1, FIGURE 10)
A(1:0) Hold Time from RISING Edge of DSTRB (only applies when ADD(1:0) = 2)
t
AHR
t
DV
t
RE
t
RD
t
CSF
t
CHR
t
R/WSF
-1
-
ns
A(1:0) to P(15:0) Data Valid Time
-
16
ns
DSTRB Low to P(15:0) Valid
-
11
ns
DSTRB Disable Time (Note 25)
-
7
ns
CE to P(15:0) Data Valid Time
-
16
ns
CE Hold Time from Rising Edge of DSTRB (only applies when ADD(1:0) = 2)
-1
-
ns
R/W Setup Time to Falling Edge of DSTRB
1
-
ns
ISL5216
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