參數(shù)資料
型號(hào): ISL5216KIZ
廠商: INTERSIL CORP
元件分類: 無(wú)繩電話/電話
英文描述: Four-Channel Programmable Digital DownConverter
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝: 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-196
文件頁(yè)數(shù): 33/65頁(yè)
文件大?。?/td> 1076K
代理商: ISL5216KIZ
33
July 8, 2005
TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES
ADD(2:0)
PINS
REGISTER DESCRIPTION
0
WR
Indirect Write Holding Register, Bits 15:0.
1
WR
Indirect Write Holding Register, Bits 31:16.
2
WR
Indirect Write Address Register for Internal Target Register (Generates a write strobe to transfer contents of the
Write Holding Register into the Target Register specified by the Indirect Address, see also Tables of Indirect
Address Registers).
3
WR
Indirect Read Address Register (Used to select the Read source of data - uses the same register as Direct
Address 2 but generates a read strobe (for RAMs and AGC) as needed instead of a write strobe).
0
RD
Indirect Read, Bits 15:0.
1
RD
Indirect Read, Bits 31:16.
2
RD
Read Register (FIFO) - Reads FIFO data from output section (This location reads output data in the order
loaded in Global Control Indirect Address Registers F820-F83F. The FIFO is automatically incremented to the
next data location at the end of each read).
3
RD
Status Register
P(15:0)
BIT DESCRIPTION
15:13
Unused.
12
BIST signature comparison result: 1= success (signatures match)
11:6
Read non-bus input pins (ENIx, RESET, SYNCI).
11 RESET (Note: This bit is inverted with respect to the RESET input pin).
10 ENIA.
9
ENIB.
8
ENIC.
7 ENID.
6
SYNCI.
5:2
Mask revision number. ISL5216 devices return 3 or higher (0, 1 and 2 were used for
HSP50216).
1
Level detector integration done. Active high.
0
New FIFO output data available (used for polling mode vs interrupt mode) Active low.
ISL5216
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