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參數(shù)資料
| 型號(hào)： | IS80C88-2 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS 8/16-Bit Microprocessor |
| 中文描述： | 16-BIT, 8 MHz, MICROPROCESSOR, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 23/32頁 |
| 文件大小： | 246K |
| 代理商： | IS80C88-2 |
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3-23
FIGURE 25. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)
NOTES:
22. Signals at 82C84A or 82C86 are shown for reference only.
23. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
24. Status inactive in state just prior to T4.
25. Cascade address is valid between first and second INTA cycles.
26. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
Waveforms
(Continued)
T1
T2
T3
T4
TW
TCLSH
(SEE NOTE 24)
TCLDX2
TCLDV
TCLAX
TCLMH
(19)
(18) TCLML
TCHDTH
(19) TCLMH
TCVNX
(36)
TCLAV
(23)
TCHSV
(21)
TCLSH
(22)
CLK
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
AD7-AD0
DEN
AMWC OR AIOWC
MWTC OR IOWC
82C88
OUTPUTS
SEE NOTES 22, 23
INTA CYCLE
A15-A8
(SEE NOTES 25, 26)
AD7-AD0
MCE/PDEN
(30) TCLMCH
DT/R
INTA
DEN
82C88 OUTPUTS
SEE NOTES 22, 23, 25
RESERVED FOR
CASCADE ADDR
(25) TCLAZ
(28) TSVMCH
T(35)
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
(18) TCLML
TCLMH (19)
TCLDX1 (7)
(18)TCLML
POINTER
INVALID ADDRESS
AD7-AD0
A15-A8
S2, S1, S0
TCHDTL
TCHSV (21)
(34)
(22)
(33)
(24)
DATA
TCVNX (36)
(6)
TDVCL
TCLMCL
(32)
(41)
(42)
TCLAV(23)
TCVNV
(35)
80C88
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