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參數(shù)資料
| 型號(hào)： | IS80C88-2 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS 8/16-Bit Microprocessor |
| 中文描述： | 16-BIT, 8 MHz, MICROPROCESSOR, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 246K |
| 代理商： | IS80C88-2 |
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3-21
(32)
TCLMCL
MCE Inactive Delay (Note 13)
-
15
-
15
ns
CL = 100pF
for all 80C88 outputs
in addition to internal
loads.
(33)
TCLDV
Data Valid Delay
10
110
10
60
ns
(34)
TCLDX2
Data Hold Time
10
-
10
-
ns
(35)
TCVNV
Control Active Delay (Note 13)
5
45
5
45
ns
(36)
TCVNX
Control Inactive Delay (Note 13)
10
45
10
45
ns
(37)
TAZRL
Address Float to Read Active
0
-
0
-
ns
(38)
TCLRL
RD Active Delay
10
165
10
100
ns
(39)
TCLRH
RD Inactive Delay
10
150
10
80
ns
(40)
TRHAV
RD Inactive to Next Address Active
TCLCL
-45
-
TCLCL
-40
-
ns
(41)
TCHDTL
Direction Control Active Delay
(Note 13)
-
50
-
50
ns
(42)
TCHDTH
Direction Control Inactive Delay
(Note 1)
-
30
-
30
ns
(43)
TCLGL
GT Active Delay
0
85
0
50
ns
(44)
TCLGH
GT Inactive Delay
0
85
0
50
ns
(45)
TRLRH
RD Width
2TCLC
L -75
-
2TCLC
L -50
-
ns
(46)
TOLOH
Output Rise Time
-
15
-
15
ns
From 0.8V to 2.0V
(47)
TOHOL
Output Fall Time
-
15
-
15
ns
From 2.0V to 0.8V
NOTES:
13. Signal at 82C84A or 82C88 shown for reference only.
14. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
15. Applies only to T2 state (8ns into T3).
16. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.
17. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
AC Electrical Specifications
V
CC
= 5.0V
±
10%; T
A
= 0
o
C to +70
o
C (C80C88, C80C88-2)
V
CC
= 5.0V
±
10%; T
A
= -40
o
C to +85
o
C (I80C88, I80C88-2)
V
CC
= 5.0V
±
10%; T
A
= -55
o
C to +125
o
C (M80C88)
V
CC
= 5.0V
±
5%;
T
A
= -55
o
C to +125
o
C (M80C88-2)
(Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
SYMBOL
PARAMETER
80C88
80C88-2
UNITS
TEST CONDITIONS
MIN
MAX
MIN
MAX
80C88
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