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參數(shù)資料
| 型號： | IS61NVP204818-166TQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | SRAM |
| 英文描述： | 2M X 18 ZBT SRAM, 3.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 221K |
| 代理商： | IS61NVP204818-166TQ |
Integrated Silicon Solution, Inc.
1
Rev. 00A
05/02/07
IS61NLP102436/IS61NVP102436
IS61NLP204818/IS61NVP204818
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control using
MODE input
Three chip enables for simple depth expansion
and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP and 165-ball PBGA
packages
Power supply:
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
Industrial temperature available
Lead-free available
DESCRIPTION
The 36 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 1M words by 36 bits and 2M words by 18 bits,
fabricated with
ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
1Mb x 36 and 2Mb x 18
36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
PRELIMINARY INFORMATION
JUNE 2007
FAST ACCESS TIME
Symbol
Parameter
-200
-166
Units
tKQ
Clock Access Time
3.1
3.5
ns
tKC
Cycle Time
5
6
ns
Frequency
200
166
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61NVP204818A-166TQLI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61NVP25636A-200B2LI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61NVP25636A-200B3LI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61NVP25636A-200TQI | 功能描述:靜態(tài)隨機(jī)存取存儲器 8Mb 256Kx36 200Mhz 2.5v I/O RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61NVP25636A-200TQI-TR | 功能描述:靜態(tài)隨機(jī)存取存儲器 8Mb 256Kx36 200Mhz 2.5v I/O RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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