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參數(shù)資料
| 型號(hào)： | IS42VS16160D-75BLI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封裝： | 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54 |
| 文件頁(yè)數(shù)： | 21/61頁(yè) |
| 文件大?。?/td> | 939K |
| 代理商： | IS42VS16160D-75BLI |
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
CLK
CKE
HIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
CS
RAS
CAS
WE
A0-A9
A10
BA0, BA1
BANK ADDRESS
A11, A12
READ COMMAND
READS
READ bursts are initiated with a READ command, as
shownintheREADCOMMANDdiagram.
Thestartingcolumnandbankaddressesareprovidedwith
theREADcommand,andautoprechargeiseitherenabledor
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theburst.ForthegenericREADcommandsusedinthefol-
lowing illustrations, auto precharge is disabled.
DuringREADbursts,thevaliddata-outelementfromthe
starting column address will be available following the
CASlatencyaftertheREADcommand.Eachsubsequent
data-outelementwillbevalidbythenextpositiveclock
edge.The CAS Latency diagram shows general timing
for each possible CAS latency setting.
Uponcompletionofaburst,assumingnoothercommands
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst
will continue until terminated. (At the end of the page, it will
wraptocolumn0andcontinue.)
DatafromanyREADburstmaybetruncatedwithasub-
sequentREADcommand,anddatafromafixed-length
READburstmaybeimmediatelyfollowedbydatafroma
READcommand.Ineithercase,acontinuousflowofdata
canbemaintained.Thefirstdataelementfromthenew
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
ThenewREADcommandshouldbeissuedx cycles before
the clock edge at which the last desired data element is
valid, where x equalstheCASlatencyminusone.Thisis
showninConsecutiveREADBurstsforCASlatenciesof
twoandthree;dataelementn +3iseitherthelastofa
burstoffourorthelastdesiredofalongerburst.The256Mb
SDRAMusesapipelinedarchitectureandthereforedoes
notrequirethe2n rule associated with a prefetch architec-
ture.AREADcommandcanbeinitiatedonanyclockcycle
followingapreviousREADcommand.Full-speedrandom
read accesses can be performed to the same bank, as
showninRandomREADAccesses,oreachsubsequent
READmaybeperformedtoadifferentbank.
DatafromanyREADburstmaybetruncatedwithasub-
sequent WRITE command, and data from a fixed-length
READburstmaybeimmediatelyfollowedbydatafroma
WRITEcommand(subjecttobusturnaroundlimitations).
TheWRITEburstmaybeinitiatedontheclockedgeim-
mediatelyfollowingthelast(orlastdesired)dataelement
fromtheREADburst,providedthatI/Ocontentioncanbe
avoided. In a given system design, there may be a pos-
sibilitythatthedevicedrivingtheinputdatawillgoLow-Z
beforetheSDRAMDQsgoHigh-Z.Inthiscase,atleast
a single-cycle delay should occur between the last read
dataandtheWRITEcommand.
TheDQMinputisusedtoavoidI/Ocontention,asshown
inFiguresRW1andRW2.TheDQMsignalmustbeas-
serted(HIGH)atleastthreeclockspriortotheWRITE
command(DQMlatencyistwoclocksforoutputbuffers)
tosuppressdata-outfromtheREAD.OncetheWRITE
commandisregistered,theDQswillgoHigh-Z(orremain
High-Z),regardlessofthestateoftheDQMsignal,provided
theDQMwasactiveontheclockjustpriortotheWRITE
commandthattruncatedtheREADcommand.Ifnot,the
secondWRITEwillbeaninvalidWRITE.Forexample,if
DQMwasLOWduringT4inFigureRW2,thentheWRITEs
atT5andT7wouldbevalid,whiletheWRITEatT6would
be invalid.
TheDQMsignalmustbede-assertedpriortotheWRITE
command(DQMlatencyiszeroclocksforinputbuffers)
to ensure that the written data is not masked.
Afixed-lengthREADburstmaybefollowedby,ortruncated
with, a PRECHARGE command to the same bank (provided
thatautoprechargewasnotactivated), and a full-page burst
maybetruncatedwithaPRECHARGEcommandtothe
samebank.ThePRECHARGEcommandshouldbeissued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minusone.ThisisshownintheREADtoPRECHARGE
Note:A9is"Don'tCare"forx16.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS45VS16160D-8BLA2 | 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| IS43R32800B-5BL | 8M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| IS61C512-25TI | x8 SRAM |
| IS61C512-35J | x8 SRAM |
| IS61C512-35JI | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42VS16400C1 | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10T | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10TL | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10TLI | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12T | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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