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參數(shù)資料
| 型號： | IS42VS16160D-75BLI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封裝： | 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54 |
| 文件頁數(shù)： | 20/61頁 |
| 文件大?。?/td> | 939K |
| 代理商： | IS42VS16160D-75BLI |
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Integrated Silicon Solution, Inc. — www.issi.com
27
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
CLK
CKE
ROW ADDRESS
BANK ADDRESS
CS
RAS
CAS
WE
A0-A12
BA0,BA1
HIGH
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
DON'T CARE
CLK
COMMAND
ACTIVE
NOP
tRCD
T0
T1
T2
T3
T4
READ or
WRITE
CHIP OPERATION
BANK/ROW ACTIVATION
BeforeanyREADorWRITEcommandscanbeissued
toabankwithintheSDRAM,arowinthatbankmustbe
“opened.”ThisisaccomplishedviatheACTIVEcommand,
which selects both the bank and the row to be activated
(see ActivatingSpecificRowWithinSpecificBank).
After opening a row (issuinganACTIVEcommand),aREAD
orWRITEcommandmaybeissuedtothatrow,subjectto
the trcdspecification.Minimumtrcd should be divided by
theclockperiodandroundeduptothenextwholenumber
to determine the earliest clock edge after the ACTIVE
commandonwhichaREADorWRITEcommandcanbe
entered.Forexample,atrcdspecificationof15nswitha
143MHzclock(7nsperiod)resultsin2.14clocks,rounded
to3.Thisisreflectedinthefollowingexample,whichcov-
ersanycasewhere2<[trcd(MIN)/tck] ≤3.(Thesame
procedure is used to convert other specification limits from
timeunitstoclockcycles).
AsubsequentACTIVEcommandtoadifferentrowinthe
same bank can only be issued after the previous active
rowhasbeen“closed”(precharged).Theminimumtime
intervalbetweensuccessiveACTIVEcommandstothe
same bank is defined by trc.
AsubsequentACTIVEcommandtoanotherbankcanbe
issued while the first bank is being accessed, which results
inareductionoftotalrow-accessoverhead.Theminimum
timeintervalbetweensuccessiveACTIVEcommandsto
different banks is defined by trrd.
EXAMPLE: MEETING TRCD (MIN) WHEN 2 < [TRCD (MIN)/TCK] ≤ 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS45VS16160D-8BLA2 | 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| IS43R32800B-5BL | 8M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| IS61C512-25TI | x8 SRAM |
| IS61C512-35J | x8 SRAM |
| IS61C512-35JI | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42VS16400C1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-10TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42VS16400C1-12T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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