- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299227 > IS42S81600A-7TI 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | IS42S81600A-7TI |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁數(shù)： | 31/65頁 |
| 文件大小： | 556K |
| 代理商： | IS42S81600A-7TI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁
38
XMEGA C3 [DATASHEET]
8361D–AVR–07/2013
21.
USB – Universal Serial Bus Interface
21.1 Features
One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
– One input endpoint per endpoint address
– One output endpoint per endpoint address
Endpoint address transfer type selectable to
– Control transfers
– Interrupt transfers
– Bulk transfers
– Isochronous transfers
Configurable data payload size per endpoint, up to 1023 bytes
Endpoint configuration and data buffers located in internal SRAM
– Configurable location for endpoint configuration data
– Configurable location for each endpoint's data buffer
Built-in direct memory access (DMA) to internal SRAM for:
– Endpoint configurations
– Reading and writing endpoint data
Ping-pong operation for higher throughput and double buffered operation
– Input and output endpoint data buffers used in a single direction
– CPU/DMA controller can update data buffer during transfer
Multipacket transfer for reduced interrupt load and software intervention
– Data payload exceeding maximum packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
Transaction complete FIFO for workflow management when using multiple endpoints
– Tracks all completed transactions in a first-come, first-served work queue
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
21.2 Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61LF51218D-8.5TQ | 512K X 18 CACHE SRAM, 8.5 ns, PQFP100 |
| IS61LPD25636A-200B2 | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD25636A-200B2I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD25636A-200B3 | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD25636A-200B3I | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S81600A-7TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S81600A-7TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S81600AL-7TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S81600B-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
| IS42S81600B-6TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。