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參數(shù)資料
| 型號： | IDT88P8344BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 38/98頁 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8344BHI |
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43
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
8.2.5 SPI-4 status channel software
The SPI-4 status channel may be configured to either LVTTL or LVDS by
loading the appropriate status channel binary file to activate the firmware.
Download LVTTL.bin when using LVTTL status mode. Download LVDS.bin
whenusingLVDSstatusmode.Thisstepshouldbeperformedasthethirdstep
in the chip configuration sequence after reset in section 8.2.1.
The download process is described.
Direct write (0x20, 0x01); /* Write register 0x20 with 0x01 to reset */
Delay at least 5ms
Direct write (0x36, 0x07);
ind_write(0x00c8, 0xdcb0);
Open LVTTL.bin or LVDS.bin file
number = file length
addr = 0x0e00;
if ( number % 2 == 0 )
number /=2;
else
number = number/2 + 1;
for ( i = 0; i < number; i ++ )
{
scr_fp.Read(ch, 2);
data = (ch[1] << 8) | ch[0];
ind_write(addr, data);
addr ++;
}
close file
ind_write(0x00c6, 0x0e00);
ind_write(0x00c8, 0xc860);
Direct write (0x36, 0x00);
8.2.6 IDT88P8344 layout guidelines
SPI-3 LAYOUT GUIDELINES
1) Series terminate SPI-3 traces that are greater than 1/2 inch in end-to-
end length. Place the series resistor as close as possible to the driver, but no
more than 1/2 inch away from the driving end. SPI-3 inputs must have ringing
controlled to prevent the SPI-3 inputs from going more than 0.5 Volts below
ground.UsetheIBISmodelsformoreaccurateresultswiththespecificdevices
being used.
2) Minimize all SPI-3 data and control trace lengths to not exceed the
T
D-MAX - TSETUP requirement. For example, if the SPI-3 clock is 104 MHz, TD-
MAX of a device is 5.65 ns, and TSETUP of the attached device is 1 ns, the maximum
PCB trace delay Table 18 permitted is 3 ns (Unit Interval - T
D-MAX- TSETUP). This
translates to a maximum PCB trace length for data and control lanes of 13.5
inches, if the loaded PCB trace delay is 220 picoseconds per inch. This is for
zero T
SETUP margin, and does not include any margin for clock driver skew.
ClockdriverorclocktraceskewcouldreducetheT
SETUP margin in this example.
3) Match all SPI-3 clock lengths to within the T
D-MIN - THOLD requirement. For
example, if T
D-MIN for the device is 1.5 ns, and THOLD for the attached device
is 0.5 ns, the worst case PCB clock trace skew for zero T
HOLD margin (defined
in this example as the maximum PCB trace delay that the SPI-3 ingress clock
of the attached device can exceed the trace delay of the SPI-3 egress clock
of the device and still meet the T
HOLD requirement of the attached device with
zero margin, assuming the fastest device [T
D-MIN ] and the worst case THOLD for
the attached device and no trace delay on the data and control lanes) is 1.7
ns (Table 15 (T
D-MIN - THOLD)), for a maximum PCB clock trace difference of
7.6 inches. Trace delay on the data and control lanes would improve the T
HOLD
margin in this example. This example does not include any margin for SPI-3
clock buffer skew.
4) Ensure a few nanoseconds of clock delay between one SPI-3 clock net
and other SPI-3 clock nets of the same frequency to minimize simultaneous
switching noise. The IDT88P8344 OCLK[3:0] outputs have skew between
each output already built in, and so are useful in lowering simultaneous
switching noise. A SPI-3 clock net is defined to be the SPI-3 egress clock for
a device and the SPI-3 ingress clock for the attached device.
5) Route all SPI-3 traces as 50 Ohm embedded stripline (inner layer
referencing ground planes). For example, 8 mil wide 1/2 oz copper traces
sandwiched between ground planes with 10 mil dielectric spacing between
ground planes and signal planes yields 52 Ohms single-ended, using FR-4
with a relative dielectric constant (
ε
R or DK) of 4.2. If the edge to edge spacing
between adjacent SPI-3 series terminated signals is 20 mils in this example,
crosstalk between adjacent signals can be kept to 2%. Use a field solver for
more accurate results.
An example timing budget Table 15, Zero Margin SPI-3 Timing budget, and
exampletracelengthstoachievetimingmarginTable16,MargincheckforSPI-
3 timing, are shown. These timing budget tables do not include clock driver
relative skew incurred if different drivers are used for a SPI-3 egress and its
attached SP-3 ingress. These tables are based on timing only and do not
include such effects as crosstalk and rise time degradation.
SPI-4 LAYOUT GUIDELINES
1) Match the P and N trace lengths within an LVDS differential signal pair to
within 100 mils or less.
2) Match the group of all differential data, control, and clock signal lengths to
within 1/2 unit interval (DDR), or less, of each other (1/4 clock period). For
SPI-3Clock
Tsetup
Thold
Td,minimum Td,maximum
Unit Interval Maximumdata Maximumdata Maximum
MaximumClock
trace delay
tracelength
clockskew
tracelength
104 MHz
1 ns
0.65 ns
2.33 ns
5.65 ns
9.6 ns
3 ns
13.5 in
1.7 ns
7.6 in
TABLE 15 - ZERO MARGIN SPI-3 TIMING BUDGET
SPI-3Clock
Tsetup
Thold
Td,minimum Td,maximum
Egress
Ingress
Longest
Shortest
Tsetup
Thold
clocktrace
datatrace
margin
104 MHz
1 ns
0.65 ns
2.33 ns
5.65 ns
4 inches
8 inches
6 inches
4 inches
2.33 ns
1.48 ns
TABLE 16 - MARGIN CHECK FOR SPI-3 TIMING
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