參數(shù)資料
型號(hào)： IDT88P8342BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 21/98頁(yè)
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHI
28
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4 egress interface port associated control
The SPI-4 interface has an associated LID to LP map (See Table 101 - SPI-
4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF)
forthepurposeofdirectingthepacketfragmentsfromtheselectedSPI-3ingress
mainmemorybuffersegmentpooltotheSPI-4egressinterface.TheSPI-4LID
map has 256 entries, one per LID. The SPI-4 interface has an enable bit. The
burst length is associated with the SPI-4 interface. The allowed burst range is
16 to 256 bytes per burst. The last burst of a packet can be shorter than the
programmed burst size.
SPI-4 egress LID associated control
Each of the 256 entries in the SPI-4 egress LID to LP map (See Table 101
-SPI-4egressLIDtoLPMap(256entries))isusedtocontrolthepullingofbursts
outofthebuffersegmentpoolandintotheSPI-4egressinterface.EachLIDcan
be enabled and disabled independently.
Figure 15. SPI-4 egress LID to LP map
6370 drwXD
LP
EN
256 LIDs
[LID] = LP | EN
Figure 16. SPI-3 ingress to SPI-4 egress datapath
The diagram below shows the datapath through the device from a SPI-3
ingress interface to the SPI-4 egress interface.
LP: Logical Port
EN: LP Enable
…
JTAG
uproc
LID Counters Memory
2 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6371 drw12
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