參數(shù)資料
型號： IDT88P8342BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 15/98頁
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHI
22
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
3.3 Microprocessor interface
- Parallel microprocessor interface
8 bit data bus for parallel operation
Byteaccess
Directaccessedspace
Indirect access space is used for most registers
Read operations to a reserved address or reserved bit fields return 0
Write operations to reserved addresses or bit fields are ignored
- Serial microprocessor interface
CompliancetoMotorolaserialprocessorinterface(SPI)specification
Byteaccess
Directaccessedspace
Indirect access space is used for most registers
Read operations to a reserved address or reserved bit fields return 0
Write operations to reserved addresses or bit fields are ignored
General purpose I/O
Five general purpose I/O pins are provided. The direction is independently
controlledbytheDIR_OUTfieldintheGPIOregister(Table123GPIORegister
(0x20)). The logical level on a pin is controlled by the LEVEL field in the GPIO
register if DIR_OUT=1, or sensed if DIR_OUT=0. The LEVEL bit monitors the
logic level of any bit selected from the indirect access space if MONITOR_EN
is set high. A bit in the indirect access space can be selected for monitoring by
the by the ADDRESS and BIT fields in the GPIO Link table (Table 124, GPIO
Monitor Table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4])).
All GPIO pins must be programmed into or out of monitor mode at the same
time.
Interrupt scheme
Events are captured in interrupt status registers. Interrupt status flags are
cleared by an microprocessor write cycle. A logical one must be written to clear
the flag(s) targeted. A two level interrupt scheme is provided comprising a
primary level and a secondary level.
The primary level identifies the secondary interrupts sources with a pending
interrupt. This information is reflected in the primary interrupt register. Interrupt
status can be enabled by associated flags both in the primary and secondary
level of the interrupt scheme.
Figure 10. Interrupt scheme
6370 drw22
event
enable
&
|
INTB
interrupted status
primary interrupt level
&
captured event
interrupted status
enable
model status
secondary interrupt level
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