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參數(shù)資料
| 型號： | IDT82V2048LBBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 160-BGA |
| 標(biāo)準(zhǔn)包裝： | 14 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BGA |
| 供應(yīng)商設(shè)備封裝： | 160-PBGA（15x15） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2048LBBG |
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IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
2.3
CLOCK EDGES
The active edge of SCLK is selectable. If pin CLKE is high, the active
edge of SCLK is the falling edge. On the contrary, if CLKE is low, the
active edge SCLK is the rising edge. Pin SDO is always active high, and
the output signals are valid on the active edge of SCLK. See Table-3
Active Clock Edge and Active Level for details. Pin CLKE is used to set
the active level for RDPn/RDNn raw slicing output: high for active high
polarity and low for active low. It should be noted that data on pin SDI
are always active high and are sampled on the rising edges of SCLK.
The data on pin TDPn or TDNn are also always active high but are
sampled on the falling edges of TCLKn, despite the level on CLKE.
2.4
RECEIVER
In receive path, the line signals couple into RRINGn and RTIPn via a
transformer and are converted into RZ digital pulses by a data slicer.
Adaptation for attenuation is achieved using an integral peak detector
that sets the slicing levels. The recovered data on pin RDPn/RDNn in an
undecoded dual rail RZ format. Loss of signal is detected. This change
in status may be enabled to generate an interrupt.
2.4.1
PEAK DETECTOR AND SLICER
The slicer determines the presence and polarity of the received
pulses. The raw positive slicer output appears on RDPn while the nega-
tive slicer output appears on RDNn. The slicer circuit has a built-in peak
detector from which the slicing threshold is derived. The slicing
threshold is default to 50% (typical) of the peak value.
Signals with an attenuation of up to 12 dB (from 2.4 V) can be recov-
ered by the receiver. To provide immunity from impulsive noise, the peak
detectors are held above a minimum level of 0.150 V typically, despite
the received signal level.
2.4.2
DATA RECOVERY
The analog line signal are converted to RZ digital bit streams on the
RDPn/RDNn pins and internally connected to an XOR which is fed to the
RCn output for external clock recovery applications.
2.4.3
LOSS OF SIGNAL (LOS) DETECTION
The Loss of Signal Detector monitors the amplitude and density of
the received signal on receiver line before the transformer (measured on
port A, B shown in Figure-7). The loss condition is reported by pulling pin
LOSn high. At the same time, LOS alarm registers track LOS condition.
When LOS is detected or cleared, an interrupt will generate if not
masked. In host mode, the detection supports the ANSI T1.231 for T1
mode, ITU G.775 and ETSI 300 233 for E1 mode. In hardware mode, it
supports the ITU G.775 and ANSI T1.231.
Table-4 summarizes the conditions of LOS. During LOS, the RDPn/
RDNn continue to output the sliced data.
Table-3 Active Clock Edge and Active Level
Pin CLKE
Pin RDPn and RDNn
Pin SDO
Slicer Output
High
Active High
SCLK
Active High
Low
Active Low
SCLK
Active High
Table-4 LOS Condition
Standard
Signal on
LOSn
ANSI T1.231 for T1
G.775 for E1
ETSI 300 233 for E1
LOS
Detected
Continuous Intervals
175
32
2048 (1 ms)
High
Amplitude(1)
1. LOS levels at device (RTIPn, RRINGn) with all ones signal. For more detail regarding the LOS parameters, please refer to Receiver Characteristics on page 38.
below typical 200 mVp
LOS
Cleared
Density
12.5% (16 marks in a sliding 128-bit
period) with no more than 99 contin-
uous zeros
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
Low
Amplitude(1)
exceed typical 250 mVp
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| IDT82V2048LDA | 功能描述:IC LIU T1/E1 8CH SHORT 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048LDAG | 功能描述:IC LIU T1/E1 8CH SHORT 144-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048S | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT WITH SINGLE ENDED OPTION |
| IDT82V2048SBB | 功能描述:IC LIU T1/E1 8CH SHORT 160-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2048SBBG | 功能描述:IC LIU T1/E1 8CH SHORT 160-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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