參數(shù)資料
型號: IDT82V2048LBBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 47/48頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 8CH SHORT 160-BGA
標準包裝: 14
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 160-BGA
供應商設備封裝: 160-PBGA(15x15)
包裝: 托盤
其它名稱: 82V2048LBBG
8
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
SDO/RDY/ACK
O83
K14
SDO: Serial Data Output
In serial host mode, the data is output on this pin. In serial write operation, SDO is always in high imped-
ance. In serial read operation, SDO is in high impedance only when SDI is in address/command byte. Data
on pin SDO is clocked out of the device on the falling edges of SCLK if pin CLKE is high, or on the rising
edges of SCLK if pin CLKE is low.
RDY: Ready Output
In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed,
while low reports the host must insert wait states.
ACK: Acknowledge Output (Active Low)
In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write operation.
INT
O
Open
Drain
82
K13
INT: Interrupt (Active Low)
This is an open drain, active low interrupt output. Two sources may cause the interrupt. Refer to 2.19 Inter-
rupt Handling for details.
D7/AD7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
D1/AD1
D0/AD0
I/O
High
Imped-
ance
28
27
26
25
24
23
22
21
K1
J1
J2
J3
J4
H2
H3
G2
Dn: Data Bus 7~0
In non-multiplexed host mode, these pins are the bi-directional data bus.
ADn: Address/Data Bus 7~0
In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.
In hardware mode, these pins should be tied to VDDIO/2.
In serial host mode, these pins should be grounded.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
TQFP144 PBGA160
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