參數(shù)資料
型號(hào)： IDT82V2048LBBG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 48/48頁(yè)
文件大小： 0K
描述： IC LIU T1/E1 8CH SHORT 160-BGA
標(biāo)準(zhǔn)包裝： 14
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 160-BGA
供應(yīng)商設(shè)備封裝： 160-PBGA（15x15）
包裝： 托盤
其它名稱： 82V2048LBBG
9
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
I
12
13
14
15
16
F4
F3
F2
F1
G3
MCn: Performance Monitor Configuration 3~0
In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select a transmitter or
receiver of channel 1 to 7 for non-intrusive monitoring. Channel 0 is used as the monitoring channel. If a
transmitter is monitored, signals on the corresponding pins TTIPn and TRINGn are internally transmitted
to RTIP0 and RRING0 pins. If a receiver is monitored, signals on the corresponding pins RTIPn and
RRINGn are internally transmitted to RTIP0 and RRING0 pins. The monitored is then output to RDP0 and
RDN0 pins.
Performance Monitor Configuration determined by MC[3:0] is shown below. Note that if MC[2:0] = 000, the
device is in normal operation of all the channels.
In host mode operation, the monitoring channel is selected in the PMON register. The signals monitored
by channel 0 can be routed to TTIP0/RING0 by activating the remote loopback in this channel (refer to
An: Address Bus 4~0
When pin MODE1 is low, the parallel host interface operates with separate address and data bus. In this
mode, the signal on this pin is the address bus of the host interface.
When pin MODE1 is high or in serial host mode, these pins should be tied to GND.
OE
I
114
E14
OE: Output Driver Enable
Pulling this pin low can drive all driver output into high impedance for redundancy application without
external mechanical relays. In this condition, all other internal circuits remain active.
CLKE
I
115
E13
CLKE: Clock Edge Select
The signal on this pin determines the active edge of RCn, RDPn, RDNn and SCLK. Refer to 2.3 Clock
Edges for details.
JTAG Signals
TRST
I
Pull-up
95
G12
TRST: JTAG Test Port Reset (Active Low)
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor
and can be left disconnected.
TMS
I
Pull-up
96
F11
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and can be left disconnected.
TCK
I
97
F14
TCK: JTAG Test Clock
The clock of the JTAG test is input on this pin. The data on TDI and TMS are clocked into the device on ris-
ing edges of TCK while the data on TDO pin is clocked out of the device on falling edges of TCK. This pin
should be connected to GNDIO or VDDIO pin when unused.
Table-1 Pin Description (Continued)
Name
Type
Pin No.
Description
TQFP144 PBGA160
MC[3:0]
Monitoring Configuration
0000
Normal operation without monitoring
0001
Monitor Receiver 1
0010
Monitor Receiver 2
0011
Monitor Receiver 3
0100
Monitor Receiver 4
0101
Monitor Receiver 5
0110
Monitor Receiver 6
0111
Monitor Receiver 7
1000
Normal operation without monitoring
1001
Monitor Transmitter 1
1010
Monitor Transmitter 2
1011
Monitor Transmitter 3
1100
Monitor Transmitter 4
1101
Monitor Transmitter 5
1110
Monitor Transmitter 6
1111
Monitor Transmitter 7
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IDT82V2048SBB 功能描述:IC LIU T1/E1 8CH SHORT 160-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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