參數(shù)資料
型號: IDT82P2916BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 94/138頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝: 84
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 3.10W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-LFBGA
供應(yīng)商設(shè)備封裝: 484-CABGA(19x19)
包裝: 托盤
包括: AIS 警報(bào)檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠(yuǎn)程檢測器和發(fā)生器
IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
59
April 24, 2010
3.6.3
MCLK, MASTER CLOCK INPUT
MCLK provides a stable reference timing for the IDT82P2916. MCLK
should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1
mode) accuracy. The clock frequency of MCLK is set by pins
MCKSEL[3:0] and can be N x 1.544 MHz or N x 2.048 MHz with 1
≤ N ≤
8 (N is an integer number). Refer to MCKSEL[3:0] pin description for
details.
If there is a loss of MCLK (duty cycle is less than 30% for 10 s), the
device will enter power down. In this case, both the receive and transmit
circuits are turned off. The pins on the line interface will be in High-Z
state. The pins on receive system interface will be in High-Z state or in
low level, as selected by the RHZ bit (b6, RCF0,...). The input on the
transmit system interface is ignored and the output on the transmit
system interface will be in High-Z state. Refer to Section 3.2.7 Receiver
If MCLK recovers after loss of MCLK the device will be reset auto-
matically.
3.6.4
XCLK, INTERNAL REFERENCE CLOCK INPUT
XCLK is derived from MCLK. For the respective channel, it is 1.544
MHz in T1/J1 mode or 2.048 MHz in E1 mode. XCLK is used as select-
able reference clock for
pattern /AIS generation
RCLKn in LLOS
Loss of TCLKn to determine Transmit Output High-Z.
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