參數(shù)資料
型號： IDT82P2916BFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 46/138頁
文件大小： 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標準包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 3.10W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器
IDT82P2916
16-CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
15
April 24, 2010
RCLKn / RMFn
(n=0~15)
Output
AB7, W4, AA3, AB2, AA7, AA17,
AB22, W18, A18, A16, A14, A12,
A11, A9, A7, E6
RCLKn: Receive Clock for Channel 0 ~ 15
When the receive system interface is configured to Single Rail NRZ Format mode, Dual Rail
NRZ Format mode or Dual Rail RZ Format mode, this multiplex pin is used as RCLKn.
RCLKn outputs a 1.544 MHz (in T1/J1 mode) or 2.048 MHz (in E1 mode) clock which is
recovered from the received signal.
The data output on RDPn/RDNn (in Receive Dual Rail NRZ Format mode, Receive Dual Rail
RZ Format mode and Receive Dual Rail Sliced) is updated on the active edge of RCLKn. The
active edge is selected by the RCK_ES bit (b4, RCF1,...).
In LLOS condition, RCLKn output high or XCLK,
as selected by the RCKH bit (b7,
,...) (refer to Section 3.5.3.1 Line LOS (LLOS) for details).
When the receiver is powered down, RCLKn will be in High-Z state or low, as selected by the
RHZ bit (b6, RCF0,...).
RMFn: Receive Multiplex Function for Channel 0 ~ 15
When the receive system interface is configured to Dual Rail Sliced mode, this multiplex pin is
used as RMFn.
(Refer to the description of RMFn of the RDNn/RMFn multiplex pin for details).
LLOS
Output
AB14
LLOS: Receive Line Loss Of Signal
LLOS synchronizes with the output of CLKE1 and can indicate the LLOS (Line LOS) status of
all 16 channels in a serial format.
When the clock output on CLKE1 is enabled, LLOS indicates the LLOS status of the 16 chan-
nels in a serial format and repeats every seventeen cycles. The start filler is positioned by
LLOS0. Refer to the description of LLOS0 below for details.
LLOS is updated on the rising edge of CLKE1 and is always active high.
When the clock output of CLKE1 is disabled, LLOS will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
LLOS0
Output
AA13
LLOS0: Receive Line Loss Of Signal for Start Position
LLOS0 can indicate the start position on the LLOS pin.
When the clock output on CLKE1 is enabled, LLOS0 pulses high for one CLKE1 clock cycle to
indicate the start position on the LLOS pin. When CLKE1 outputs 8 KHz clock, LLOS0 pulses
high for one 8 KHz clock cycle (125 s) every seventeen 8 KHz clock cycles; when CLKE1
outputs 2.048 MHz clock, LLOS0 pulses high for one 2.048 MHz clock cycle (488 ns) every
seventeen 2.048 MHz clock cycles. LLOS0 is updated on the rising edge of CLKE1.
When the clock output on CLKE1 is disabled, LLOS0 will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
Name
I / O
Pin No.
Description
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