Inband Loopback (IB) Detection T" />
參數(shù)資料
型號： IDT82P2821BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 98/151頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 21+1CH 640-PBGA
標準包裝： 5
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應商設備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
包括： 缺陷和警報檢測，驅動器過流檢測和保護，LLOS 檢測，PRBSARB / IB 檢測和生成
其它名稱： 82P2821BH
IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
50
February 6, 2009
Inband Loopback (IB) Detection
The IB detection is in compliance with ANSI T1.403.
The extracted data is used to compare with the target IB code. The
length of the target activate/deactivate IB code can be 3 to 8 bits, as
determined by the IBAL[1:0]/IBDL[1:0] bits (b3~2/b1~0, IBL,...). The
content of the target activate/deactivate IB code is programmed in the
IBA[7:0]/IBD[7:0] bits (b7~0, IBDA/IBDD,...). Refer to Figure-29.
Figure-29 IB Detection
During comparison, if the extracted data coincides with the target
activate/deactivate IB code with no more than 10-2 bit error rate for a
certain period, the IB code is detected. The period depends on the
setting of the AUTOLP bit (b3, LOOP,...).
If the AUTOLP bit (b3, LOOP,...) is ‘0’, Automatic Digital/Remote
Loopback is disabled. In this case, when the activate IB code is detected
for more than 40 ms, the IBA_S bit (b1, STAT1,...) will be set to indicate
the activate IB code detection; when the deactivate IB code is detected
for more than 40 ms (T1/J1 mode) / 30 ms (E1 mode), the IBD_S bit (b0,
STAT1,...) will be set to indicate the deactivate IB code detection.
If the AUTOLP bit (b3, LOOP,...) is ‘1’, Automatic Digital/Remote
Loopback is enabled. In this case, when the activate IB code is detected
for more than 5.1 seconds, the IBA_S bit (b1, STAT1,...) will be set to
indicate the activate IB code detection. The detection of the activate IB
code in the receive path will activate Remote Loopback or the detection
of the activate IB code in the transmit path will activate Digital Loopback
Loopback). When the deactivate IB code is detected for more than 5.1
seconds, the IBD_S bit (b0, STAT1,...) will be set to indicate the deacti-
vate IB code detection. The detection of the deactivate IB code in the
receive path will deactivate Remote Loopback or the detection of the
deactivate IB code in the transmit path will deactivate Digital Loopback
A transition from ‘0’ to ‘1’ on the IBA_S/IBD_S bit (b1/b0, STAT1,...)
or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the IBA_S/IBD_S bit
(b1/b0, STAT1,...) will set the IBA_IS/IBD_IS bit (b1/b0, INTS1,...) to ‘1’
respectively, as selected by the IB_IES bit (b0, INTES,...). When the
IBA_IS/IBD_IS bit (b1/b0, INTS1,...) is ‘1’, an interrupt will be reported
on INT if not masked by the IBA_IM/IBD_IM bit (b1/b0, INTM1,...).
3.5.6
ERROR COUNTER
An internal 16-bit Error Counter is used to count one of the following
errors:
LBPV: BPV/CV detected in the receive path (line side);
LEXZ: EXZ detected in the receive path (line side);
LBPV + LEXZ: BPV/CV and EXZ detected in the receive path (line
side);
SBPV: BPV/CV detected in the transmit path (system side) (dis-
abled in Transmit Single Rail NRZ Format mode);
SEXZ: EXZ detected in the transmit path (system side);
SBPV + SEXZ: BPV/CV and EXZ detected in the transmit path
(system side) (disabled in Transmit Single Rail NRZ Format
mode);
PRBS/ARB error.
The CNT_SEL[2:0] bits (b4~2, ERR,...) select one of the above
errors to be counted.
The Error Counter is buffered. It is updated automatically or manu-
ally, as determined by the CNT_MD bit (b1, ERR,...).
The Error Counter is accessed by reading the ERRCH and ERRCL
registers.
3.5.6.1 Automatic Error Counter Updating
When the CNT_MD bit (b1, ERR,...) is ‘1’, the Error Counter is
updated every one second automatically.
The one-second timer uses MCLK as clock reference. The expiration
of each one second will set the TMOV_IS bit (b0, INTTM) and induce an
interrupt reported by INT if not masked by the TMOV_IM bit (b0, GCF).
When each one second expires, the Error Counter transfers the
accumulated error numbers to the ERRCH and ERRCL registers and
the Error Counter will be cleared to start a new round counting. The
ERRCH and ERRCL registers should be read in the next second, other-
wise they will be overwritten.
When the ERRCH and ERRCL registers are all ‘1’s and there is still
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
The process of automatic Error Counter updating is illustrated in
from Rx path
or Tx path
Decoding
Target code -
length & content
programming
Comparison
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