參數(shù)資料
型號(hào): IDT82P2821BH
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/151頁
文件大?。?/td> 0K
描述: IC LIU T1/J1/E1 21+1CH 640-PBGA
標(biāo)準(zhǔn)包裝: 5
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
包括: 缺陷和警報(bào)檢測,驅(qū)動(dòng)器過流檢測和保護(hù),LLOS 檢測,PRBSARB / IB 檢測和生成
其它名稱: 82P2821BH
IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
100
February 6, 2009
PG - Pattern Generation Control Register
Address: 010H, 050H, 090H, 0D0H, 110H, 150H, 190H, 1D0H, (CH1~CH8)
210H, 250H, 290H, 2D0H, 310H, 350H, 390H, 3D0H, (CH9~CH16)
410H, 450H, 490H, 4D0H, 510H, (CH17~CH21)
7D0H (CH0)
Type: Read / Write
Default Value: 00H
Bit
Name
Description
7-
Reserved.
6
PG_CK
This bit selects the reference clock when the pattern (including PRBS, ARB & IB) is generated.
When the pattern is generated in the receive path:
0: XCLK. (default)
1: Recovered clock from the received signal.
When the pattern is generated in the transmit path:
0: XCLK. (default)
1: Transmit clock, i.e., the clock input on TCLKn (in Transmit Single Rail NRZ Format mode and in Transmit Dual Rail NRZ For-
mat mode) or the clock recovered from the data input on TDPn and TDNn (in Transmit Dual Rail RZ Format mode)
5 - 4
PG_EN[1:0]
These bits select the pattern to be generated.
00: Disable. (default)
01: PRBS.
10: ARB.
11: IB.
3
PG_POS
This bit selects the pattern (including PRBS, ARB & IB) generation direction.
0: Transmit path. (default)
1: Receive path.
2
PAG_INV
This bit controls whether to invert the generated PRBS/ARB pattern.
0: Normal. (default)
1: Invert.
1 - 0
PRBG_SEL[1:0] These bits are valid only when the PRBS pattern is generated. They select the PRBS pattern.
00: 220 - 1 QRSS. (default)
01: 215 - 1 PRBS.
1X: 211 - 1 PRBS.
7654321
0
-
PG_CK
PG_EN1
PG_EN0
PG_POS
PAG_INV
PRBG_SEL1
PRBG_SEL0
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