參數(shù)資料
型號: IDT79RC32T351-100DH
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 41/42頁
文件大?。?/td> 0K
描述: IC MPU 32BIT CORE 100MHZ 208-QFP
產(chǎn)品變化通告: Product Discontinuation 07/Dec/2009
標準包裝: 24
系列: Interprise™
處理器類型: RISC 32-位
速度: 100MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 79RC32T351-100DH
8 of 42
May 25, 2004
IDT 79RC32351
GPIOP[24]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: ATM receive PHY address, RXADDR[0].
GPIOP[25]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
1st Alternate function: ATM receive PHY address, RXADDR[1].
2nd Alternate function: Active DMA channel code, DMAP[1].
GPIOP[26]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
GPIOP[27]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus address, MADDR[22].
GPIOP[28]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus address, MADDR[23].
GPIOP[29]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus address, MADDR[24].
GPIOP[30]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus address, MADDR[25].
GPIOP[31]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
1ST Alternate function: DMA finished, DMAFIN.
2nd Alternate function: EJTAG/ICE reset, EJTAG_TRST_N.
GPIOP[32]
I/O
High Drive General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin.
GPIOP[33]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin.
GPIOP[34]
I/O
High Drive General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin.
GPIOP[35]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as an auxiliary general purpose I/O pin.
DMA
DMAFIN
O
Low
External DMA finished. This signal is asserted low by the RC32351 when the number of bytes specified in the DMA
descriptor have been transferred to or from an external device.
Primary function: General Purpose I/O, GPIOP[31]. At reset, this pin defaults to primary function GPIOP[31].
2nd Alternate function: EJTAG_TRST_N.
DMAREQN
I
STI
External DMA Device Request. The external DMA device asserts this pin low to request DMA service.
Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18].
DMADONEN
I
STI
External DMA Device Done. The external DMA device asserts this signal low to inform the RC32351 that it is done with
the current DMA transaction.
Primary function: General purpose I/O, GPIOP[19]. At reset, this pin defaults to primary function GPIOP[19].
USB
USBCLKP
I
STI
USB Clock. 48 MHz clock input used as time base for the USB interface.
USBDN
I/O
USB
USB D- Data Line. This is the negative differential USB data signal.
USBDP
I/O
USB
USB D+ Data Line. This is the positive differential USB data signal.
USBSOF
O
Low Drive USB start of frame.
Primary function: General Purpose I/O, GPIOP[20]. At reset, this pin defaults to primary function GPIOP[20].
Ethernet
MIICOLP
I
STI
MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected.
MIICRSP
I
STI
MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.
MIIMDCP
O
Low Drive MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management inter-
face.
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 4 of 7)
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