– Supports burst transfers ◆ USB – Revision 1.1 compliant – USB slave device controller
參數(shù)資料
型號(hào): IDT79RC32T351-100DH
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 12/42頁(yè)
文件大小: 0K
描述: IC MPU 32BIT CORE 100MHZ 208-QFP
產(chǎn)品變化通告: Product Discontinuation 07/Dec/2009
標(biāo)準(zhǔn)包裝: 24
系列: Interprise™
處理器類型: RISC 32-位
速度: 100MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 79RC32T351-100DH
2 of 42
May 25, 2004
IDT 79RC32351
– Supports burst transfers
USB
– Revision 1.1 compliant
– USB slave device controller
– Supports a 6th USB endpoint
– Full speed operation at 12 Mb/s
– Supports control, interrupt, bulk and isochronous endpoints
– Supports USB remote wakeup
– Integrated USB transceiver
EJTAG
– Run-time Mode provides a standard JTAG interface
– Real-Time Mode provides additional pins for real-time trace
information
Ethernet
– Full duplex support for 10 and 100 Mb/s Ethernet
– IEEE 802.3u compatible Media Independent Interface (MII)
with serial management interface
– IEEE 802.3u auto-negotiation for automatic speed selection
– Flexible address filtering modes
– 64-entry hash table based multicast address filtering
ATM SAR
– Can be configured as one UTOPIA level 1 interface or 1
UTOPIA level 2 interface with 2 address lines (3 PHYs max)
– Supports 25Mb/s and faster ATM
– Supports UTOPIA data path interface operation at speeds up
to 33 MHz
– Supports standard 53-byte ATM cells
– Performs HEC generation and checking
– Cell processing discards short cells and clips long cells
– 16 cells worth of buffering
– UTOPIA modes: 8 cell input buffer and 8 cell output buffer
– Hardware support for CRC-32 generation and checking for
AAL5
– Hardware support for CRC-10 generation and checking
– Virtual caching receive mechanism supports reception of any
length packet without CPU intervention on up to eight simulta-
neously active receive channels
– Frame Mode transmit mechanism supports transmission of
any length packet without CPU intervention
System Features
– JTAG interface (IEEE Std. 1149.1 compatible)
– 208 pin PQFP package
– 2.5V core supply and 3.3V I/O supply
– Up to 133 MHz pipeline frequency and up to 66 MHz bus
frequency
Figure 2 Example of xDSL Residential Gateway Using RC32351
Ethernet Transceiver
MII I/F
DMA
Channels
USB
Timers
UART
Interrupt Ctl
RC32300 CPU Core
Data Buffers
SDRAM Ctl
Memory &
I/O Controller
ATM I/F
Ethernet MAC
Ethernet to PC
Clock
SDRAM
Memory & I/O
Transmission
Convergence
Data Pump
AFE
USB to PC
Debug port
32-bit Data Bus
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