參數(shù)資料
型號(hào)： IDT79RC32T333-100DHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 29/30頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT CORE 100MHZ 208-QFP
產(chǎn)品變化通告： Product Discontinuation 07/Dec/2009
標(biāo)準(zhǔn)包裝： 24
系列： Interprise™
處理器類型： RISC 32-位
速度： 100MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
包裝： 托盤
其它名稱： 79RC32T333-100DHI
8 of 30
May 4, 2004
IDT 79RC32333
sdram_cs_n[3:0]
Output
H
High
SDRAM Chip Select Negated Bus Recommend an external pull-up.
SDRAM mode: Provides chip select to each SDRAM bank.
SODIMM mode: Provides upper select byte enables [7:4].
sdram_s_n[1:0]
Output
H
High
SDRAM SODIMM Select Negated Bus
SDRAM mode: Not used.
SDRAM SODIMM mode: Upper and lower chip selects.
sdram_bemask_n
[3:0]
Output
H
High
SDRAM Byte Enable Mask Negated Bus (DQM)
SDRAM mode: Provides byte enables for each byte lane of all DRAM banks.
SODIMM mode: Provides lower select byte enables [3:0].
sdram_245_oe_n
Output
H
Low
SDRAM FCT245 Output Enable Negated Recommend an external pull-up.
SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both
reads and writes to any DRAM bank.
sdram_245_dt_r_n
Output
Z
High
SDRAM FCT245 Direction Transmit/Receive Recommend an external pull-up.
Uses cpu_dt_r_n. See CPU Core Specific Signals below.
On-Chip Peripherals
dma_ready_n[0]
I/O
Z
Low
DMA Ready Negated Bus Requires an external pull-up.
Ready mode: Input pin for general purpose DMA channel 0 that can initiate the next datum in the current
DMA descriptor frame.
Done mode: Input pin for general purpose DMA channel 0 that can terminate the current DMA descriptor
frame.
dma_ready_n[0] 1st Alternate function PIO[0]; 2nd Alternate function: dma_done_n[0].
pio[7:0]
I/O
See
related
pins
Low
Programmable Input/Output
General purpose pins that can each can be configured as a general purpose input or general purpose
output. These pins are multiplexed with other pin functions:
pci_gnt_n[1] (pci_eeprom_cs), spi_mosi, spi_sck, spi_ss_n, spi_miso, uart_rx[0], uart_tx[0],
dma_ready_n[0]. Note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time.
The others default to inputs.
uart_rx[0]
I/O
Z
Low
UART Receive Data Bus
UART mode: UART channel receive data.
uart_rx[0] Alternate function: PIO[2].
uart_tx[0]
I/O
Z
Low
UART Transmit Data Bus Recommend an external pull-up.
UART mode: UART channel send data. Note that this pin defaults to an input at reset time and must be
programmed via the PIO interface before being used as a UART output.
uart_tx[0] Alternate function: PIO[1].
spi_mosi
I/O
L
Low
SPI Data Output
Serial mode: Output pin from RC32333 as an Input to a Serial Chip for the Serial data input stream.
In PCI satellite mode, acts as an Output pin from RC32333 that connects as an Input to a Serial Chip for
the Serial data input stream for loading PCI Configuration Registers in the RC32333 Reset Initialization
Vector PCI boot mode.
1st Alternate function: PIO[6]. Defaults to the output direction at reset time.
2nd Alternate function: pci_eeprom_mdo.
spi_miso
I/O
Z
Low
SPI Data Input
Serial mode: Input pin to RC32333 from the Output of a Serial Chip for the Serial data output stream.
In PCI satellite mode, acts as an Input pin from RC32333 that connects as an output to a Serial Chip for
the Serial data output stream for loading PCI Configuration Registers in the RC32333 Reset Initialization
Vector PCI boot mode. Defaults to input direction at reset time.
1st Alternate function: PIO[3].
2nd Alternate function: pci_eeprom_mdi.
Name
Type
Reset
State
Status
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 4 of 6)
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