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參數(shù)資料
| 型號： | IDT74SSTUAE32866ABFG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/30頁 |
| 文件大小： | 0K |
| 描述： | IC BUFFER 25BIT CONF REG 96-BGA |
| 標準包裝： | 3,000 |
| 邏輯類型： | 1:2 可配置寄存緩沖器 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 位數(shù)： | 25，14 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 96-LFBGA |
| 供應商設備封裝： | 96-CABGA（13.5x5.5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74SSTUAE32866ABFG8 |
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DATASHEET
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUAE32866A
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
IDT74SSTUAE32866A
7120/5
Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is
designed for 1.425V to 1.575V VDD operation.
The control inputs are LVCMOS. All outputs are 1.5-V
CMOS drivers that have been optimized to drive the DDR-II
DIMM load. IDT74SSTUAE32866A operates from a
differential clock (CLK and CLK). Data are registered at the
crossing of CLK going high, and CLK going low.
The C0 input controls the pinout configuration of the 1:2
pinout from A configuration (when low) to B configuration
(when high). The C1 input controls the pinout configuration
from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0,
C12 = 1)
Parity that arrives one cycle after the data input to which it
applies is checked on the PAR_IN of the first register. The
second register produces to PPO and QERR signals. The
QERR of the first register is left floating. The valid error
information is latched on the QERR output of the second
register. If an error occurs QERR is latched low for two
cycles or until RESET is low.
B - Single Configuration (C0 = 0, C1 = 0)
The device supports low-power standby operation. When
the RESET input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs are forced low. The LVCMOS RESET and Cn inputs
must always be held at a valid logic high or low level. To
ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
In the DDR-II RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the IDT74SSTUAE32866A must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The device monitors both DCS and CSR inputs and will
gate the Qn outputs from changing states when both DCS
and CSR inputs are high. If either DCS and CSR input is
low, the Qn outputs will function normally. The RESET input
has priority over the DCS and CSR control and will force the
outputs low. If the DCS-control functionality is not desired,
then the CSR input can be hardwired to ground, in which
case, the setup-time requirement for DCS would be the
same as for the other D data inputs. Package options
include 96-ball LFBGA (MO-205CC).
Features
Supports 1.5V VDD operation for DDR2 DIMMs
25-bit 1:1 or 14-bit 1:2 registered buffer with parity check
functionality
Supports LVCMOS switching levels on C0, C1, and
RESET inputs
Low voltage operation: VDD = 1.425V to 1.575V
Available in 96-ball LFBGA package
Applications
DDR2 Memory Modules running at 1.5V VDD
Provides complete DDR DIMM solution with
ICS98UAE877A
Ideal for DDR2 667
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74SSTUBF32865ABK | 功能描述:IC BUFFER 28BIT 1:2 REG 160-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| IDT74SSTUBF32865ABK8 | 功能描述:IC BUFFER 28BIT 1:2 REG 160-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| IDT74SSTUBF32865ABKG | 功能描述:IC BUFFER 28BIT 1:2 REG 160-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| IDT74SSTUBF32865ABKG8 | 功能描述:IC BUFFER 28BIT 1:2 REG 160-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| IDT74SSTUBF32866BBFG | 功能描述:IC BUFFER 25BIT REG DDR2 96-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
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