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| 型號： | IDT7005L55J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | Dual, Ultra Low Cost, RRIO CMOS Amplifier; Package: MSOP; No of Pins: 8; Container: Tape & Reel |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 55 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 189K |
| 代理商： | IDT7005L55J |
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
12
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l &
Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.Min.Max.Min.Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
17
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
17
____
20
____
20
ns
tBAC
BUSY Acce ss Time from Chip Enable Low
____
15
____
17
____
20
____
20
ns
tBDC
BUSY Acce ss Time from Chip Enable High
____
15
____
17
____
17
____
17
ns
tAPS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
18
____
18
____
30
____
30
ns
tWH
Write Hold After
BUSY(5)
12
____
13
____
15
____
17
____
ns
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
0
____
ns
tWH
Write Hold After
BUSY(5)
12
____
13
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay
(1)
____
30
____
30
____
45
____
50
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
25
____
25
____
35
____
35
ns
2738 tbl 15a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind &
Military
7005X70
Military
Only
Symbol
Parameter
Min.Max.Min.Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
45
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
40
____
40
ns
tBAC
BUSY Acce ss Time from Chip Enable Low
____
20
____
40
____
40
ns
tBDC
BUSY Acce ss Time from Chip Enable High
____
20
____
35
____
35
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Date(3)
____
35
____
40
____
45
ns
tWH
Write Hold After
BUSY(5)
25
____
25
____
25
____
ns
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After
BUSY(5)
25
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay
(1)
____
60
____
80
____
95
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
45
____
65
____
80
ns
2738 tbl 15b
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005L55J8 | 功能描述:IC SRAM 64KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7005L55JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L55JI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 68PLCC |
| IDT7005L55JI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 55NS 68PLCC |
| IDT7005L55L68 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
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