參數(shù)資料
型號(hào)： IDT5V49EE901NLGI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 35/36頁(yè)
文件大?。?/td> 0K
描述： IC PLL CLK GEN 200MHZ 32VFQFN
產(chǎn)品培訓(xùn)模塊： VersaClock™ III Programmable Clocks
特色產(chǎn)品： VersaClock III Timing Devices
標(biāo)準(zhǔn)包裝： 2,500
系列： VersaClock™ III
類(lèi)型： 時(shí)鐘發(fā)生器，多路復(fù)用器
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： HCSL，LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:9
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-VFQFPN 裸露焊盤(pán)（4x4）
包裝： 帶卷 (TR)
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
8
IDT5V49EE901
REV R 092412
values range from 1 to 6. Values of 0 and 7 should not be
used.
SS_OFFSET[5:0]
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of ±0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
SD[3:0]
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the
bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 2)
NSSC = NSSC[2:0] * 2 (Eq. 3)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)
where SJ is the unencoded sample out of a possible 12 and
SDK is the delta-encoded sample out of a possible 12.
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
if 1 < Amplitude < 2, then set X2 bit to '1'.
Modulation frequency:
FPFD = FIN / D (Eq. 6)
FVCO = FPFD * MNOM (Eq. 7)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)
Spread:
ΣΔ = SD0 + SD1 + SD2 + …+ SD11
the number of samples used depends on the NSSC value
ΣΔ< 63 - SS_OFFSET
(
ΣΔ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5V49EE901PGGI 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR
IDT5V49EE901PGGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28TSSOP
IDT5V49EE902-EVB 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V49EE902
IDT5V49EE902NLGI 功能描述:IC CLOCK GEN PLL 500MHZ 32VFQFPN RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱(chēng):844S012AKI-01LFT
IDT5V49EE902NLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN
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