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參數(shù)資料
| 型號(hào)： | IDT5V49EE901NLGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 32VFQFN |
| 產(chǎn)品培訓(xùn)模塊： | VersaClock™ III Programmable Clocks |
| 特色產(chǎn)品： | VersaClock III Timing Devices |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | VersaClock™ III |
| 類型： | 時(shí)鐘發(fā)生器，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-VFQFPN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
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IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
4
IDT5V49EE901
REV R 092412
OUT2
11
8
O
Adjustable1
Configurable clock output 2. Single-ended or differential
when combined with OUT1.
OUT3
24
O
Adjustable1
Configurable clock output 3. Single-ended or differential
when combined with OUT6.
OUT4
13
10
O
Adjustable1,2
Configurable clock output 4. Single-ended or differential
when combined with OUT4b.
OUT4b
14
11
O
Adjustable1,2
Configurable clock output 4b. Single-ended or differential
when combined with OUT4.
OUT5
16
14
O
Adjustable1,2
Configurable clock output 5. Single-ended or differential
when combined with OUT5b.
OUT5b
17
15
O
Adjustable1,2
Configurable clock output 5b. Single-ended or differential
when combined with OUT5.
OUT6
23
O
Adjustable1
Configurable clock output 6. Single-ended or differential
when combined with OUT3.
VDD
3, 7,
12, 25
1, 9, 12,
16, 25,
32
Power
Device power supply. Connect to 3.3V.
VDDx
4
Power
Crystal oscillator power supply. Connect to 3.3V through
5
Ωresistor. Use filtered analog power supply if available.
AVDD
21
Power
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
GND
9, 15,
22
6, 13,
17, 22,
31,PAD
Power
Connect to Ground.
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
3. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
4. Each power pin should have a dedicated 0.01F de-coupling capacitor. Digital VDDs may be tied together.
5. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
Pin Name
PG28
Pin#
NL32
Pin#
I/O
Pin Type
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V49EE901PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V49EE901PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28TSSOP |
| IDT5V49EE902-EVB | 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V49EE902 |
| IDT5V49EE902NLGI | 功能描述:IC CLOCK GEN PLL 500MHZ 32VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V49EE902NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
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