參數(shù)資料
型號(hào): IDT5T93GL161PFI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 5T SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封裝: TQFP-64
文件頁(yè)數(shù): 2/14頁(yè)
文件大?。?/td> 153K
代理商: IDT5T93GL161PFI8
INDUSTRIALTEMPERATURERANGE
10
IDT5T93GL161
2.5VLVDS1:16GLITCHLESSCLOCKBUFFERTERABUFFERII
FSEL Operation for When Opposite Clock Dies
NOTES:
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the SEL pin should be toggled
and FSEL asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
than or equal to the minimum DC differential specified in the datasheet.
FSEL Operation for When Current Clock Dies
NOTES:
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should
be asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
than or equal to the minimum DC differential specified in the datasheet.
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