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參數(shù)資料
| 型號(hào)： | ICSSSTVA32852CHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 |
| 封裝： | LEAD FREE, BGA-114 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 147K |
| 代理商： | ICSSSTVA32852CHLF-T |
4
ICSSSTVA32852
0918A—04/30/04
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
VDDQ
MIN
TYP
MAX
UNITS
VIK
II = -18mA
2.3V
-1.2
IOH = -100A
2.3V - 2.7V
VDDQ - 0.2
IOH = -16mA
2.3V
2.05
IOL = 100A
2.3V - 2.7V
0.2
IOL = 16mA
2.3V
0.20
II
All Inputs
VI = VDD or GND
2.7V
±5
A
Standby (Static)
RESET# = GND
0.01
A
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET# = VDD
40
mA
Dynamic operating
(clock only)
RESET# = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK# switching
50% duty cycle.
35
A/clock
MHz
Dynamic Operating
(per each data input)
RESET# = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
7
A/ clock
MHz/data
rOH
Output High
2.3V - 2.7V
12
rOL
Output Low
2.3V - 2.7V
10
rO(D)
[rOH - rOL] each
separate bit
2.5V
4
Data Inputs
2.5
3.5
CLK and CLK#
2.5
3.5
Notes:
1. Guaranteed by design, not 100% tested in production.
Ci
IOL = 20mA
IO = 20mA, TA = 25°C
VOH
VOL
IDD
IDDD
IO = 0
CONDITIONS
2.5V
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
pF
IOH = -20mA
V
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