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參數(shù)資料
| 型號： | ICS9DB202BG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 209K |
| 代理商： | ICS9DB202BG |
9DB202BG
www.icst.com/products/hiperclocks.html
FEBRUARY 6, 2004
1
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS,
ZERO DELAY BUFFER/JITTER ATTENUATOR
ADVANCE INFORMATION
GENERAL DESCRIPTION
The ICS9DB202 is a high performance 1-to-2
Differential-to HCSL Zero Delay Buffer/Jitter
Attenuator designed for use in PCI Express
systems. In some PCI Express systems, such as
those found in desktop PCs, the PCI Express
clocks are generated from a low bandwidth, high
phase noise PLL frequency synthesizer. In these systems, a
zero delay buffer may be required to attenuate high frequency
random and deterministic jitter components from the PLL
synthesizer and from the system board. The ICS9DB202 has 2
PLL bandwidth modes. In low bandwidth mode, the PLL loop
BW is about 500KHz and this setting will attenuate the most
jitter from the reference clock input while being high enough to
pass a triangular input spread spectrum profile. There is also a
high bandwidth mode which sets the PLL bandwidth at 1MHz
which will pass more spread spectrum modulation.
Because many serdes that are available as of the date of this
writing (August 2003) have x10 reference multipliers rather
than x12.5 multipliers, 1 of the 2 PCI Express outputs
(PCIEX1:2) can be set for 125MHz rather than 100MHz by
using the FS0 and FS1 pins. Output PCIX0 will always run at
the reference clock frequency (usually 100MHz in desktop
PC PCI Express Applications.
Features
2 0.7V current mode differential HCSL output pairs
1 differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Output skew: 50ps (maximum)
Cycle-to-cycle jitter: 50ps (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
HiPerClockS
ICS
PIN ASSIGNMENT
nOE0
nCLK
CLK
BYPASS
nOE1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
BLOCK DIAGRAM
ICS9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
package body
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
The Advance Information presented herein represents a product currently in design or being considered for design. The noted characteristics are
design targets. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
Phase
Detector
VCO
Loop
Filter
1 HiZ
0 Enabled
1 HiZ
0 Enabled
0 ÷4
1 ÷5
0 ÷5
1 ÷4
FS0
FS1
Internal Feedback
÷5
Current
Set
-
+
0
1
0
1
IREF
PLL_BW
CLK
nCLK
FS0
VDD
GND
PCIEXT0
PCIEXC0
VDD
nOE0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD_A
BYPASS
IREF
FS1
VDD
GND
PCIEXT1
PCIEXC1
VDD
nOE1
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| ICS9DB202CFLFT | 功能描述:IC JITTER ATTENUATOR 20-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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