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參數(shù)資料
| 型號(hào)： | IDTQS5930-50TQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5930 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 67K |
| 代理商： | IDTQS5930-50TQ |
1
INDUSTRIALTEMPERATURERANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
R
D
Q
Q0
R
D
Q
Q1
R
D
Q
Q2
R
D
Q
Q3
R
D
Q
Q4
R
D
Q
Q/2
0
1
0
/2
VCO
LOO P
FILTER
PH AS E
DETE CTO R
FREQ _SEL
FEED BACK
SYNC
PLL_EN
OE/RST
Q
SEPTEMBER 2000
2000
Integrated Device Technology, Inc.
DSC-5849/1
c
QS5930T
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
5V operation
Q/2 output, 5 Q outputs
Useful for Pentium, PowerPC, and PCI systems
Internal loop filter RC network
Low noise TTL level outputs
<250ps rising edge output skew
Balanced drive outputs ±24mA
PLL bypass feature for low frequency testing
Internal VCO/2 option for wider frequency range
Outputs tri-state and reset while OE/
RST is low
ESD > 2000V
Latch up > -300mA
Available in QSOP package
DESCRIPTION
The QS5930T Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q0–Q4, Q/2. Careful layout and design ensure < 250ps
skew between the Q0–Q4, and Q/2 outputs. The QS5930T includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5930T is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe sys-
tems. Several can be used in parallel or scattered throughout a sys-
tem for guaranteed low skew, system-wide clock distribution networks.
In the QSOP package, the QS5930T clock driver represents the best
value in small form factor, high-performance clock management prod-
ucts.
For more information on PLL clock driver products, see Application
Note AN-227.
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