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參數(shù)資料
| 型號： | IDTQS5930-50TQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5930 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 67K |
| 代理商： | IDTQS5930-50TQ |
4
INDUSTRIALTEMPERATURERANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input
frequencies.
5. tPD measured at device inputs at 1.5V, Q output at 28MHz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter (1)
Min.
Max.
Unit
tSKR
Output Skew Between Rising Edges, Q0-Q4 (and Q/2) (2)
—
250
ps
tSKF
Output Skew Between Falling Edges, Q0-Q4 (and Q/2) (2)
—
350
ps
tPW
Pulse Width, Q0-Q4, Q/2 outputs, 80MHz
TCY/2
0.5
TCY/2 + 0.5
ns
tJ
Cycle-to-Cycle Jitter, FI > 33MHz ( 4)
—
250
ns
tPD
SYNC Input to Feedback Delay ( 5)
100
+400
ps
tPZH
tPZL
Output Enable Time, OE/
RST LOW to HIGH ( 3)
07
ns
tPHZ
tPLZ
Output Disable Time, OE/
RST HIGH to LOW ( 3)
06
ns
tR, tF
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
ns
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