參數(shù)資料
型號(hào): ICS84314AY-02LFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 9/23頁(yè)
文件大?。?/td> 0K
描述: IC SYNTHESIZER 700MHZ 32-LQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: HiPerClockS™
類型: 頻率合成器
PLL: 帶旁路
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 84314AY-02LFT
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
IDT / ICS 3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
17
ICS84314AY-02 REV. A MARCH 24, 2009
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors C14 and C15 as close as possible
to the power pins. If space allows, placing the decoupling capacitor
at the component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
CCA shares the same power supply with VCC, insert the RC filter
R7, C11, and C16 in between. Place this RC filter as close to the
V
CCA as possible.
Clock Traces and Termination
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system
failure. In the synchronous high-speed digital system, the clock
signal is less tolerable to poor signal quality than other signals. Any
ringing on the rising or falling edge or excessive ring back can
cause system failure. The trace shape and the trace delay might be
restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal
traces.
The traces with 50
transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
Keep the clock trace on the same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace can
affect the trace characteristic impedance and hence
degrade signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace and
the other signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in this
example.
Crystal
The crystal X1 should be located as close as possible to the pins
25 (XTAL_IN) and 26 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
Figure 8B. PCB Board Layout for ICS84314-02
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