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參數(shù)資料
| 型號(hào)： | ICS1894KI-32LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 45/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII，RMII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-VFQFPN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 800-2030-6 |
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
5
ICS1894-32
REV M 021512
Strapping Options
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
Functional Description
The ICS1894-32 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
Physical Coding sublayer (PCS)
Physical Medium Attachment sublayer (PMA)
Physical Medium Dependent sublayer (PMD)
Auto-Negotiation sublayer
The ICS1894-32 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-32 can interface directly with the MAC via MII/RMII
interface signals.
The ICS1894-32 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
Pin
Number
Pin
Name
Pin
Type1
Pin Function
14
AMDIX/RXD3
IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
15
P3/RXD2
IO/Ipd
The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
11
P2/INT
IO/Ipd
31
P0/LED0
IO
32
P1/ISO/LED1
IO
16
RXTRI/RXD1
IO/Ipd
1 = Real time receiver isolation function enable3; 0 = Receiver Tristate Disable
17
FDPX/RXD0
IO/Ipu
1=Full duplex
0=Half duplex (mode not supported)
Ignored if Auto negotiation is enabled
18
RMII/RXDV
IO/Ipd
1 = RMII mode
0 = MII mode
20
ANSEL/RXCLK
IO/Ipu
1=Enable auto negotiation
0=Disable auto negotiation
21
NOD/RXER
IO/Ipd
0=Node mode
1=repeater mode (mode not supported)
22
SPEED/TXCLK
IO/Ipu
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1894KI-33LF | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-33LFT | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-34LF | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-34LFT | 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN |
| ICS1894KI-40LF | 功能描述:PHYCEIVER LOW PWR 3.3V 40QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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