參數(shù)資料
型號： ICS1894KI-32LFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 15/50頁
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： PHYceiver™
類型： PHY 收發(fā)器
規(guī)程： MII，RMII
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-VFQFPN 裸露焊盤（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 800-2030-6
ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
22
ICS1894-32
REV M 021512
8.3
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
8.2
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
8.1
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
8.0
Message code field
/Unformatted code field
Bit value depends on the
particular message
Bit value depends on the
particular message
RO
–
0
Register
9 through 15 - Reserved by IEEE
Register
16 - Extended Control Register
16.15
Command Override
Write enable
Disabled
Enabled
RW
SC
0
–
16.14
ICS reserved
Reserved
RW/0
–
0
16.13
ICS reserved
Reserved
RW/0
–
0
16.12
ICS reserved
Reserved
RW/0
–
0
16.11
ICS reserved
Reserved
RW/0
–
0
–
16.10
PHY Address Bit 4
RO
–
0
16.9
PHY Address Bit 3
RO
–
0
16.8
PHY Address Bit 2
RO
–
L
16.7
PHY Address Bit 1
RO
–
L
–
16.6
PHY Address Bit 0
RO
–
L
16.5
Stream Cipher Test
Mode
Normal operation
Test mode
RW
–
0
16.4
ICS reserved
Reserved
RW/0
–
16.3
NRZ/NRZI encoding
NRZ encoding
NRZI encoding
RW
–
1
8
16.2
Transmit invalid codes
Disabled
Enabled
RW
–
0
16.1
ICS reserved
Reserved
RW/0
–
0
16.0
Stream Cipher disable
Stream Cipher enabled
Stream Cipher disabled
RW
–
0
Register
17 - Quick Poll Detailed Status Register
17.15
Data rate
10 Mbps
100 Mbps
RO
–
17.14
Duplex
Half duplex (mode not
supported)
Full duplex
RO
–
17.13
Auto-Negotiation
Progress Monitor Bit 2
Reference Decode Table
RO
LM
X
0
17.12
Auto-Negotiation
Progress Monitor Bit 1
Reference Decode Table
RO
LM
X
0
Bit
Definition
When Bit = 0
When Bit = 1
Access 2
SF2
Default3
Hex
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1894KI-33LF 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-33LFT 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-34LF 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-34LFT 制造商:Integrated Device Technology Inc 功能描述:PHYCEIVER LOW PWR 3.3V 32QFN
ICS1894KI-40LF 功能描述:PHYCEIVER LOW PWR 3.3V 40QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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