參數(shù)資料
型號: ICS1523M
英文描述: High-Performance Programmable Line-Locked Clock Generator
中文描述: 高性能可編程線鎖定時鐘發(fā)生器
文件頁數(shù): 2/27頁
文件大?。?/td> 1216K
代理商: ICS1523M
ICS1523
2
Document Revision History
Rev P (First Release)
Pin Descriptions changed to add type column. (pg 3)
Added SDA and AC Input Characteristics. (pg 18)
Changed VCO Output, Intrinsic Jitter graph to show slow and fast cases (pg 19)
Timing diagram changes to reference t0 to REF and notes on test conditions added (pg 22)
Lock Renamed Lock/Ref (Throughout).
General cleanup for readability.
Rev Q
Added typical external loop filter values. (pg 17)
Added section on power supply considerations and SSTL_3 outputs. (pg 18)
Correct labels and scale on VCO Output, Intrinsic Jitter graph. (pg 20)
Correct depiction of timing diagram and added typical transition timing. (pg 23)
Added Document Revision History. (pg 25)
Rev R
Change to descriptions for pins 20 to 23. (pg 3)
Change to description for Reg 0h bits 0 and 1, added table. (pg 6)
Within table for Reg 0h bits 6 and 7, changed Osc_En to IN_SEL . (pg 6)
Moved Reg 0 bits 4 through 7 from pg 6 to new pg 7.
Change to Software Programming Flow diagram. (pg 13).
Added under Absolute Maximum Ratings ESD ratings and warning. (pg 19)
Under Recommend Operating Conditions, PECL Outputs, Output Low Voltage, added a note and added a new page. (pg 19)
Under Recommend Operating Conditions, SSTL-3 Outputs, Output Low Voltage, changed direction of symbols. (pg 19)
Change to VCO Output Frequency and Intrinsic Jitter graph to reflect correct VCO frequency (pg 20)
Rev S
Moved Revision History from last page of data sheet to second page. (pg 2)
In Layout Guideline 2, changed shunt capacitor value from 150 pF to 33 pF. (pg 19)
Changed various cross-references within Layout Guidelines. (pg 19)
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