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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 39 of 71
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed
Units
Notes
-68
-75A
-260
-360
Operating Current
I
CC1
1 bank operation
t
RC
= t
RC
(min), t
CK
= min
Active-Precharge command
cycling without burst operation
75
75
70
70
mA
1, 2
Precharge Standby Cur-
rent in Power Down
Mode
I
CC2P
CKE
≤
V
IL
(max), t
CK
= min,
CS = V
IH
(min)
1
1
1
1
mA
7
I
CC2PS
CKE
≤
V
IL
(max), t
CK
= Infinity,
CS = V
IH
(min)
1
1
1
1
mA
7
Precharge Standby Cur-
rent in Non-Power Down
Mode
I
CC2N
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
40
35
25
25
mA
4
I
CC2NS
CKE
≥
V
IH
(min), t
CK
= Infinity,
6
6
6
6
mA
6
No Operating Current
(Active state: 4 bank)
I
CC3N
CKE
≥
V
IH
(min), t
CK
= min,
CS = V
IH
(min)
45
40
30
30
mA
4
I
CC3P
CKE
≤
V
IL
(max), t
CK
= min,
3
3
3
3
mA
5, 7
Operating Current (Burst
Mode)
I
CC4
t
CK
= min,
Read/ Write command cycling,
Multiple banks active, gapless
data, BL = 4
135
120
90
90
mA
2, 3
Auto (CBR) Refresh Cur-
rent
I
CC5
t
CK
= min, t
RC
= t
RC
(min)
CBR command cycling
150
145
140
140
mA
7
Self Refresh Current
I
CC6
CKE
≤
0.2V
SP
1
1
1
1
mA
7
LP
400
400
400
400
μ
A
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed up to three times during t
RC
(min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during t
CK
(min).
4. Input signals are changed once during three clock cycles.
5. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
6. Input signals are stable.
7. SP: Standard power; LP: Low power.