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參數資料
| 型號： | IBMN364404CT3C-260 |
| 英文描述： | x4 SDRAM |
| 中文描述： | x4內存 |
| 文件頁數： | 23/71頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | IBMN364404CT3C-260 |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 23 of 71
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank separately or all banks simultaneously. Three
address bits, A10, A12, and A13, are used to define which bank(s) is to be precharged when the command is
issued.
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For
write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command
can be issued. This delay is known as t
DPL
, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (t
RP
).
Burst Write with Auto-Precharge Interrupted by Read
Bank Selection for Precharge by Address Bits
A10
Bank Select
Precharged Bank(s)
LOW
BS0, BS1
Single bank defined by BS0, BS1
HIGH
DON’T CARE
All Banks
DIN A
0
COMMAND
NOP
NOP
*
NOP
WRITE A
Auto-Precharge
DIN A
1
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
t
CK3,
DQs
CAS latency = 3
Bank A can be reactivated at completion of t
DAL
.
*
Number of clocks required depends on clock cycle
time and speed sort.
READ B
DIN A
2
NOP
DOUT B
0
DOUT B
1
DOUT B
2
t
DAL
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
相關PDF資料 |
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| IBMN364804CT3C-360 | x8 SDRAM |
| IBMN364804CT3C-75A | x8 SDRAM |
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