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參數資料
| 型號： | IBMN364164CT3C-260 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內存 |
| 文件頁數： | 3/71頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | IBMN364164CT3C-260 |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 71
Pin Description
CLK
Clock Input
DQ0-DQ15
Data Input/Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS (CS0, CS1)
Chip Select
V
DD
Power (+3.3V)
RAS
Row Address Strobe
V
SS
Ground
CAS
Column Address Strobe
V
DDQ
Power for DQs (+3.3V)
WE
Write Enable
V
SSQ
Ground for DQs
BS1, BS0 (A12, A13)
Bank Select
NC
No Connection
A0 - A11
Address Inputs
—
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
CLK
Input
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Active
High
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Active Low
CS enables the command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
RAS, CAS,
WE
Input
Active Lowbe executed by the SDRAM.
BS1, BS0
(A12, A13)
Input
—
Selects which bank is to be active.
A0 - A11
Input
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BS0 and BS1 are used to define which bank to precharge.
DQ0 - DQ15
Input-
Output
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively.
In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an out-
put enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode,
DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is
low but blocks the write operation if DQM is high.
V
DD
, V
SS
Supply
—
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise immunity.
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