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| 型號： | IBMN364164CT3C-260 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 18/71頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | IBMN364164CT3C-260 |
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IBMN364164
IBMN364404
64Mb Synchronous DRAM - Die Revision C
IBMN364804
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 18 of 71
19L3265.E35856B
1/01
Burst Stop Command
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the
burst operation prematurely. These methods include using another Read or Write Command to interrupt an
existing burst operation or using a Precharge Command to interrupt a burst cycle and close the active bank.
When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention.
If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the active bank.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is
defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state
after a delay which is equal to the CAS Latency set in the Mode Register.
If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the
burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Termination of a Burst Read Operation
Termination of a Burst Write Operation
COMMAND
READ A
NOP
NOP
NOP
Burst
Stop
NOP
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
The burst ends after a delay equal to the CAS latency.
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
(Burst Length = Full Page, CAS Latency = 2, 3)
COMMAND
NOP
WRITE A
NOP
NOP
Burst
Stop
NOP
NOP
NOP
NOP
DIN A
0
DIN A
1
DIN A
2
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
DQs
CAS latency = 2,3
(Burst Length = Full Page, CAS latency = 2, 3)
: “H” or “L”
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| IBMN364404CT3C-360 | x4 SDRAM |
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