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參數(shù)資料
| 型號： | I4K-L67142V-55 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, CQCC48 |
| 封裝： | LCC-48 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 178K |
| 代理商： | I4K-L67142V-55 |
L67132/L67142
Rev. D (19 Fev. 97)
3
MATRA MHS
Pin Names
LEFT PORT
RIGHT PORT
NAMES
CSL
CSR
Chip select
R/WL
R/WR
Write Enable
OEL
OER
Output Enable
A0L – 10L
A0R – 10R
Address
I/O0L – 7L
I/O0R – 7R
Data Input/Output
BUSYL
BUSYR
Busy Flag
VCC
Power
GND
Ground
Functional Description
The L67132/67142 has two ports with separate control,
address and I/0 pins that permit independent read/write
access to any memory location. These devices have an
automatic power-down feature controlled by CS. CS
controls on-chip power-down circuitry which causes the
port concerned to go into stand-by mode when not
selected (CS high). When a port is selected access to the
full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE
turns
the
Output
drivers
on
when
set
LOW.
Non-conflicting READ/WRITE conditions are illustrated in
table 1.
Arbitration Logic
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns and
determine which port has access. In all cases, an active
BUSY flag will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously.Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
logic arbitrates between CSL and CSR for access ; or (2)
if the CS are low before an address match, on-chip control
logic arbitrates between the left and right addresses for
access (refer to table 2). The inhibited port’s BUSY flag
is set and will reset when the port granted access
completes its operation in both arbitration modes.
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 16 or more bits in a
dual-port RAM system means that several chips may be
active simultaneously. If every chip has a hardware
arbitrator, and the addresses for each chip arrive at the
same time one chip may activate its L BUSY signal while
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out” problem, MHS has
developed a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to
the MASTER with no external components, giving a
speed advantage over other systems.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until the
BUSY input has been settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation. On the
opposite, the write pulse must extend a hold time beyond
BUSY to ensure that a write cycle occurs once the conflict
is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the
same time.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
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