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| 型號(hào)： | I4K-L67142V-55 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, CQCC48 |
| 封裝： | LCC-48 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | I4K-L67142V-55 |
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L67132/L67142
Rev. D (19 Fev. 97)
10
MATRA MHS
AC Parameters
SYMBOL
PARAMETER
L67132–45
L67142–45
L67132–55
L67142–55
L67132–70
L67142–70
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
BUSY TIMING (For L 67132 only)
tBAA
BUSY Access time to address
–
35
–
45
–
50
ns
tBDA
BUSY Disable time to address
–
35
–
40
–
40
ns
tBAC
BUSY Access time to Chip Select
–
30
–
35
–
50
ns
tBDC
BUSY Disable time to Chip Select
–
25
–
30
–
40
ns
tWDD
Write Pulse to data delay (40)
–
70
–
80
–
90
ns
tDDD
Write data valid to read data delay (40)
–
45
–
55
–
70
ns
tAPS
Arbitration priority set–up time (41)
5
–
5
–
5
–
ns
tBDD
BUSY disable to valid data
–
Note 42
–
Note 42
–
Note 42
ns
BUSY TIMING (For L 67142 only)
tWB
Write to BUSY input (43)
0
–
0
–
0
–
ns
tWH
Write hold after BUSY (44)
20
–
30
–
30
–
ns
tWDD
Write pulse to data delay (45)
–
70
–
80
–
90
ns
tDDD
Write data valid to read data delay (45)
–
45
–
55
–
70
ns
Notes :
40. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with
BUSY (For L67132 only)”.
41. To ensure that the earlier of the two ports wins.
42. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
43. To ensure that the write cycle is inhibited during contention.
44. To ensure that a write cycle is completed after contention.
45. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read
with Port to port delay (For L67142 only)”.
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