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參數(shù)資料
| 型號(hào)： | I4K-L67142V-55 |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 2K X 8 DUAL-PORT SRAM, 55 ns, CQCC48 |
| 封裝： | LCC-48 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | I4K-L67142V-55 |
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L67132/L67142
Rev. D (19 Fev. 97)
11
MATRA MHS
Timing Waveform of Read with BUSY (46, 47, 48) (For L 67132)
Notes :
46. To ensure that the earlier of the two port wins.
47. Write cycle parameters should be adhered to, to ensure proper writing.
48. Device is continuously enabled for both ports.
49. OE at L for the reading port.
Timing Waveform of Write with Port-to-port (50, 51, 52) (For L 67142 only)
Notes :
50. Assume BUSY = H for the writing port, and OE = L for the reading port.
51. Write cycle parameters should be adhered to, to ensure proper writing.
52. Device is continuously enabled for both ports.
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