- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385438 > HYS72T64301HP (QIMONDA) 240-Pin Registered DDR2 SDRAM Modules PDF資料下載
參數(shù)資料
| 型號： | HYS72T64301HP |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 240針DDR2 SDRAM的注冊模塊 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大?。?/td> | 1068K |
| 代理商： | HYS72T64301HP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Internet Data Sheet
Rev. 1.0, 2006-10
09152006-R5MQ-5KS2
27
HYS72T64301HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 20
Definitions for
I
DD
Self-Refresh Current
CKE
≤
0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
I
DD6
current values are guaranteed up to
T
CASE
of 85
°
C max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out
= 0 mA.
1)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V
2)
I
DD
specifications are tested after the device is properly initialized and
I
DD
parameter are specified with ODT disabled.
3) Definitions for
I
DD
see
Table 20
4)
I
DD1
,
I
DD4R
and
I
DD7
current measurements are defined with the outputs disabled (
I
OUT
= 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
I
DD2P
6) For details and notes see the relevant QIMONDA component data sheet
I
DD6
—
I
DD7
—
Parameter
Description
LOW
STABLE
FLOATING
SWITCHING
V
IN
≤
V
IL(ac).MAX
, HIGH is defined as
V
IN
≥
V
IH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are
V
REF
=
V
DDQ
/2
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Parameter
Symbol
Note
1)2)
3)4)5)6)
相關PDF資料 |
PDF描述 |
|---|---|
| HYS72T64301HP-3.7-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3S-A | 240-Pin Registered DDR2 SDRAM Modules |
| IPS0151 | FULLY PROTECTED POWER MOSFET SWITCH |
| IPS0151S | FULLY PROTECTED POWER MOSFET SWITCH |
| IPS0151STRR | SINGLE MOSFET DRIVER|MOS|SIP|3PIN|PLASTIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64301HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64400HFA | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T64400HFA-2.5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T64400HFA-3.7-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復。