參數(shù)資料
型號(hào)： HYS72T64301HP-3S-A
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝： GREEN, DIMM-240
文件頁(yè)數(shù)： 23/42頁(yè)
文件大?。?/td> 1068K
代理商： HYS72T64301HP-3S-A
Internet Data Sheet
Rev. 1.0, 2006-10
09152006-R5MQ-5KS2
23
HYS72T64301HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Average periodic refresh Interval
t
REFI
—
—
7.8
3.9
—
μ
s
μ
s
ns
14)15)
16)18)
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
t
RFC
17)
t
RP
t
RP
t
RPRE
t
RPST
t
RRD
t
RP
+ 1
t
CK
15 + 1
t
CK
0.9
0.40
7.5
10
7.5
0.25 x
t
CK
0.40
15
—
—
1.1
0.60
—
—
—
—
0.60
—
ns
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
ns
14)
14)
14)18)
16)20)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
t
RTP
t
WPRE
t
WPST
t
WR
19)
WR
t
WR
/
t
CK
—
t
CK
20)
t
WTR
t
XARD
7.5
2
—
—
ns
t
CK
21)
22)
t
XARDS
6 – AL
—
t
CK
22)
t
XP
2
—
t
CK
t
XSNR
t
XSRD
t
RFC
+10
200
—
—
ns
t
CK
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V. See notes
5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
8) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (
t
,
t
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for
t
CL
and
t
CH
).
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)
6)7)
Min.
Max.
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