參數(shù)資料
型號(hào): HYS72T64301HP-3S-A
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Registered DDR2 SDRAM Modules
中文描述: 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝: GREEN, DIMM-240
文件頁數(shù): 17/42頁
文件大小: 1068K
代理商: HYS72T64301HP-3S-A
Internet Data Sheet
Rev. 1.0, 2006-10
09152006-R5MQ-5KS2
17
HYS72T64301HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 14
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
t
CK
Parameter
Symbol
Min.
Max.
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3.75
45
60
15
15
8
8
8
70000
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
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