參數(shù)資料
型號(hào)： HYS72T512022HR
廠商： QIMONDA
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 240針DDR2 SDRAM的注冊(cè)模塊
文件頁數(shù)： 23/41頁
文件大?。?/td> 1063K
代理商： HYS72T512022HR
Internet Data Sheet
Rev. 1.2, 2007-01
03292006-AYVF-ZIIJ
23
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2-400
12) MIN (
t
CL
,
t
CH
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for
t
CL
and
t
CH
).
13) The
t
HZ
,
t
RPST
and
t
LZ
,
t
RPRE
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
t
), or begins driving (
t
t
).
t
and
t
transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85
°
C
and 95
°
C.
15) 0 °C
≤
T
CASE
≤
85
°
C
16) 85
°
C
<
T
CASE
≤
95
°
C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
t
timing parameter depends on the page size of the DRAM organization. See
Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4
.
19) The maximum limit for the
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum
t
WTR
is two clocks when operating the DDR2-SDRAM at frequencies
≤ 200 ΜΗ
z.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD
can be used. In “l(fā)ow active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS
has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the
t
timing parameter, where
WR
[cycles] =
t
(ns)/
t
(ns) rounded
up to the next integer value.
t
= WR + (
t
/
t
). For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Parameter
Symbol
DDR2–400
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
t
AC
t
CCD
t
CH
t
CKE
t
CL
t
DAL
–600
2
0.45
3
0.45
WR +
t
RP
+600
—
0.55
—
0.55
—
ps
t
CK
t
CK
t
CK
t
CK
t
CK
8)21)
t
DELAY
t
IS
+
t
CK
+
t
IH
—
ns
9)
t
DH
(base)
275
—
ps
10)
t
DH1
(base)
–25
—
ps
11)
t
DIPW
t
DQSCK
t
DQSL,H
t
DQSQ
0.35
–500
0.35
—
—
+
500
—
350
t
CK
ps
t
CK
ps
11)
t
DQSS
t
DS
(base)
– 0.25
150
+ 0.25
—
t
CK
ps
11)
相關(guān)PDF資料
PDF描述
HYS72T512022HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
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HYS72T512341HHP 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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