參數(shù)資料
型號: HYS72D64320GBR-5-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: 184 - Pin Registered Double Data Rate SDRAM Modules
中文描述: 184 -引腳注冊雙倍數(shù)據(jù)速率SDRAM模塊
文件頁數(shù): 25/48頁
文件大小: 844K
代理商: HYS72D64320GBR-5-B
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Data Sheet
25
Rev. 1.1, 2004-04
10102003-01E2-HPA8
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
1.0 V/ns , slow slew rate
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
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