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參數(shù)資料
| 型號： | HYS72D64320GBR-5-B |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184 - Pin Registered Double Data Rate SDRAM Modules |
| 中文描述： | 184 -引腳注冊雙倍數(shù)據(jù)速率SDRAM模塊 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 844K |
| 代理商： | HYS72D64320GBR-5-B |
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HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Data Sheet
24
Rev. 1.1, 2004-04
10102003-01E2-HPA8
Address and control input
setup time
t
IS
0.6
—
0.75
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold
time
t
IH
0.6
0.75
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
0.7
0.8
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
t
RAS
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-
refresh command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
t
RAP
t
RPRE
t
RPST
0.9
0.4
40
55
1.1
0.6
70E+3
0.9
0.4
42
60
1.1
0.6
70E+3
—
0.90
0.4
45
65
1.1
0.6
70E+3 ns
—
t
CK
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
RC
ns
2)3)4)5)
t
RFC
65
72
—
75
—
ns
2)3)4)5)
t
RCD
t
RP
15
15
t
RCD
or
t
RASmin
10
—
—
18
18
t
RCD
or
t
RASmin
12
—
—
20
20
t
RCD
or
t
RASmin
15
—
—
—
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery
+ precharge time
Internal write to read
command delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
t
RRD
—
—
—
ns
2)3)4)5)
t
WR
t
DAL
15
—
—
15
—
—
15
—
—
ns
t
CK
2)3)4)5)
2)3)4)5)11)
t
WTR
2
—
1
—
1
—
t
CK
2)3)4)5)
t
XSNR
75
—
75
—
75
—
ns
2)3)4)5)
t
XSRD
200
—
200
—
200
—
t
CK
2)3)4)5)
t
REFI
—
7.8
—
7.8
—
7.8
μ
s
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Table 12
Parameter
AC Timing - Absolute Specifications –5/–6/–7
(cont’d)
Symbol
–5
–6
–7
Unit Note/ Test
Condition
1)
DDR400B
Min.
DDR333
Min.
DDR266A
Min.
Max.
Max.
Max.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D64320GBR-5-C | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64320GBR-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184 - Pin Registered Double Data Rate SDRAM Modules |
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