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參數(shù)資料
| 型號(hào)： | HYMP112S64MP8-E3 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | SCREW LOCKS MALE |
| 中文描述： | 128M X 64 DDR DRAM MODULE, 0.6 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, DIMM-200 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | HYMP112S64MP8-E3 |
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HYMP112S64(L)MP8
Rev. 0.1/ July 2004
13
- continued -
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G821(L)M).
2.
0°
C
≤
TCASE
≤ 85
°
C
3. 85
°
C
＜
TCASE
≤ 95
°
C
Parameter
Symbol
DDR2 400
DDR2 533
Unit
Note
Min
Max
Min
Max
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
Address and control input hold time
tWPRE
tIH
0.25
600
-
-
0.25
500
-
-
tCK
ps
Address and control input setup time
Read preamble
tIS
600
0.9
-
500
0.9
-
ps
tCK
tRPRE
1.1
1.1
Read postamble
Auto-Refresh to Active/Auto-Refresh
command period
Row Active to Row Active Delay
tRPST
tRFC
0.4
105
0.6
-
0.4
105
0.6
-
tCK
ns
tRRD
7.5
-
7.5
-
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
15
2
15
tCK
ns
-
-
Auto Precharge Write Recovery +
Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
tCK
Write to Read Command Delay
tWTR
10
-
7.5
-
ns
Internal read to precharge command delay
Exit self refresh to a non-read command
tRTP
tXSNR
7.5
7.5
ns
ns
tRFC + 10
tRFC + 10
Exit self refresh to a read command
Exit precharge power down to any non-
read command
tXSRD
tXP
200
2
-
-
200
2
-
-
tCK
tCK
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
tXARD
tXARDS
2
2
tCK
tCK
6 - AL
6 - AL
t
CKE
3
3
tCK
t
AOND
t
AON
2
2
2
2
tCK
ODT turn-on
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
ns
ODT turn-on(Power-Down mode)
t
AONPD
tAC(min)+2
2tCK+
tAC(max)+1
2.5
tAC(max)+
0.6
2.5tCK+
tAC(max)+1
tAC(min)+2
2tCK+
tAC(max)+1
2.5
tAC(max)+
0.6
2.5tCK+
tAC(max)+1
ns
ODT turn-off delay
t
AOFD
2.5
2.5
tCK
ODT turn-off
t
AOF
tAC(min)
tAC(min)
ns
ODT turn-off (Power-Down mode)
t
AOFPD
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
tDelay
tIS+tCK+tIH
tIS+tCK+tIH
ns
Average periodic Refresh Interval
tREFI
tREFI
-
-
7.8
3.9
-
-
7.8
3.9
us
us
2
3
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|---|---|
| HYMP112S64MP8-E4 | SCREW LOCKS FEMALE SETS |
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| HYS72D64300HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMP112S64MP8-E4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR2 SDRAM SO-DIMM |
| HYMP112U64CP8-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-Y5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
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