參數(shù)資料
型號: HYMP112S64MP8-E3
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: SCREW LOCKS MALE
中文描述: 128M X 64 DDR DRAM MODULE, 0.6 ns, ZMA200
封裝: ROHS COMPLIANT, DIMM-200
文件頁數(shù): 10/17頁
文件大?。?/td> 405K
代理商: HYMP112S64MP8-E3
HYMP112S64(L)MP8
Rev. 0.1/ July 2004
10
PIN Capacitance
(VDD=1.8V,VDDQ=1.8V, TA=25
℃.
f=1MHz )
Note :
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
IDD Specifications
Parameter
Pin
Symbol
Min,
Max,
Unit
Input Capacitance
CK0, /CK0
CCK
15
33
pF
Input Capacitance
CKE0, /CS
CI1
44
65
pF
Input Capacitance
Address, /RAS, /CAS, /WE
CI2
27
65
pF
Input Capacitance
DQ,DM,DQS, /DQS
CIO
8
12
pF
HYMP112S64(L)MP8
PC2 3200
PC2 4300
Unit
Note
Parameter
Symbol
max.
max.
Operating one bank active-precharge current
IDD0
920
1040
mA
Operating one bank active-read-precharge
current
IDD1
1000
1120
mA
Precharge power-down current
IDD2P
48
64
mA
Precharge quiet standby current
IDD2Q
520
600
mA
Precharge standby current
IDD2N
560
640
mA
Active power-down current
IDD3P(F)
240
320
mA
IDD3P(S)
48
64
mA
Active Standby Current
IDD3N
720
840
mA
Operating burst read current
IDD4R
1320
1440
mA
Operating Current
IDD4W
1320
1440
mA
Burst auto refresh current
IDD5B
1560
1600
mA
Self Refresh Current
IDD6
80
80
mA
IDD6(L)
48
48
mA
Operating bank interleave read current
IDD7
1960
2160
mA
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